Commit 1bec5bff authored by Jeffrey Lee's avatar Jeffrey Lee

Enable part two of the FIQ fix

Detail:
  This enables support for the code which handles split transactions in the FIQ handler. This requires some extra logic to allow the FIQ handler to gracefully terminate its state machine when we need to release our hold on the FIQ vector.
  c/dwc_otg_riscos - Update FIQ claim/release functions to initialise and terminate fiq_split_enable. Make FIQ usage bools static const as nothing needs to change them at runtime.
  h/dwc_otg_riscos - Remove unused use_fiq_fix extern
  dwc/driver/c/dwc_otg_hcd_intr - Modify fiq_hcintr_handle() to allow for graceful termination - when terminating, suppress adding new xfers to the schedule and instead force the IRQ handler to deal with them
Admin:
  Tested on Raspberry Pi
  Thrashing Service_ClaimFIQ/Service_ReleaseFIQ didn't result in any obvious problems while split xfers were occuring


Version 0.16. Tagged as 'DWCDriver-0_16'
parent db8357fa
/* (0.15) /* (0.16)
* *
* This file is automatically maintained by srccommit, do not edit manually. * This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1. * Last processed by srccommit version: 1.1.
* *
*/ */
#define Module_MajorVersion_CMHG 0.15 #define Module_MajorVersion_CMHG 0.16
#define Module_MinorVersion_CMHG #define Module_MinorVersion_CMHG
#define Module_Date_CMHG 19 Jun 2014 #define Module_Date_CMHG 08 Jul 2014
#define Module_MajorVersion "0.15" #define Module_MajorVersion "0.16"
#define Module_Version 15 #define Module_Version 16
#define Module_MinorVersion "" #define Module_MinorVersion ""
#define Module_Date "19 Jun 2014" #define Module_Date "08 Jul 2014"
#define Module_ApplicationDate "19-Jun-14" #define Module_ApplicationDate "08-Jul-14"
#define Module_ComponentName "DWCDriver" #define Module_ComponentName "DWCDriver"
#define Module_ComponentPath "mixed/RiscOS/Sources/HWSupport/USB/Controllers/DWCDriver" #define Module_ComponentPath "mixed/RiscOS/Sources/HWSupport/USB/Controllers/DWCDriver"
#define Module_FullVersion "0.15" #define Module_FullVersion "0.16"
#define Module_HelpVersion "0.15 (19 Jun 2014)" #define Module_HelpVersion "0.16 (08 Jul 2014)"
#define Module_LibraryVersionInfo "0:15" #define Module_LibraryVersionInfo "0:16"
...@@ -103,14 +103,16 @@ struct dwc_otg_driver_module_params { ...@@ -103,14 +103,16 @@ struct dwc_otg_driver_module_params {
int32_t adp_enable; int32_t adp_enable;
}; };
bool use_fiq_fix = true; /* True if we're allowed to use the FIQ fix */ static const bool use_fiq_fix = true; /* True if we're allowed to use the FIQ fix */
static const bool use_fiq_split_fix = true; /* True if we're allowed to use the FIQ split xfer fix */
bool reclaim_fiq_vector = false; /* True if we should attempt to claim FIQs (i.e. driver is initialised and use_fiq_fix) */ bool reclaim_fiq_vector = false; /* True if we should attempt to claim FIQs (i.e. driver is initialised and use_fiq_fix) */
bool own_fiq_vector = false; /* True if we currently own the FIQ vector */ bool own_fiq_vector = false; /* True if we currently own the FIQ vector */
extern bool fiq_fix_enable; extern bool fiq_fix_enable,fiq_split_enable,fiq_split_schedule_enable;
extern volatile uint8_t *dwc_regs_base; extern volatile uint8_t *dwc_regs_base;
extern mphi_regs_t c_mphi_regs; extern mphi_regs_t c_mphi_regs;
extern void *dummy_send; extern void *dummy_send;
extern int complete_sched[MAX_EPS_CHANNELS];
static uint32_t fiq_stack[512]; static uint32_t fiq_stack[512];
...@@ -782,6 +784,9 @@ void dwc_otg_riscos_try_use_fiqs(dwc_softc_t *softc, bool need_to_claim) ...@@ -782,6 +784,9 @@ void dwc_otg_riscos_try_use_fiqs(dwc_softc_t *softc, bool need_to_claim)
/* Flag to DWC that the FIQ code is enabled */ /* Flag to DWC that the FIQ code is enabled */
fiq_fix_enable = use_fiq_fix; fiq_fix_enable = use_fiq_fix;
/* Also enable the split xfer fix */
fiq_split_enable = fiq_split_schedule_enable = use_fiq_split_fix;
/* Flag that we own the vector, and should reclaim it if we lose it */ /* Flag that we own the vector, and should reclaim it if we lose it */
own_fiq_vector = reclaim_fiq_vector = true; own_fiq_vector = reclaim_fiq_vector = true;
...@@ -792,8 +797,24 @@ void dwc_otg_riscos_release_fiq(dwc_softc_t *softc) ...@@ -792,8 +797,24 @@ void dwc_otg_riscos_release_fiq(dwc_softc_t *softc)
{ {
dprintf(("","Releasing FIQ vector\n")); dprintf(("","Releasing FIQ vector\n"));
/* Release our claim on the FIQ vector */
int flags; int flags;
/* If the split FIQ fix is enabled then we must do a staged release to
allow it to gracefully terminate its state machine */
if(fiq_split_enable)
{
/* Prevent new split xfers from being scheduled for completion by the FIQ handler. The IRQ handler will handle them instead. */
fiq_split_schedule_enable = false;
/* Wait for existing xfers to leave the FIQ schedule */
for(int i=0;i<MAX_EPS_CHANNELS;i++)
while(complete_sched[i] != -1)
{
dprintf(("","Waiting for complete_sched[%d]...\n",i));
}
dprintf(("","complete_sched is clear\n"));
}
/* Release our claim on the FIQ vector */
local_irq_save(flags); local_irq_save(flags);
local_fiq_disable(); local_fiq_disable();
...@@ -801,7 +822,7 @@ void dwc_otg_riscos_release_fiq(dwc_softc_t *softc) ...@@ -801,7 +822,7 @@ void dwc_otg_riscos_release_fiq(dwc_softc_t *softc)
_swix (OS_Hardware, _INR(8,9), 0, EntryNo_HAL_FIQDisableAll); _swix (OS_Hardware, _INR(8,9), 0, EntryNo_HAL_FIQDisableAll);
/* Flag to DWC that the FIQ code is no longer active */ /* Flag to DWC that the FIQ code is no longer active */
fiq_fix_enable = false; fiq_fix_enable = fiq_split_enable = false;
/* Flag that we no longer own the vector */ /* Flag that we no longer own the vector */
own_fiq_vector = false; own_fiq_vector = false;
......
...@@ -57,6 +57,7 @@ void * dummy_send; ...@@ -57,6 +57,7 @@ void * dummy_send;
mphi_regs_t c_mphi_regs; mphi_regs_t c_mphi_regs;
#ifdef __riscos #ifdef __riscos
volatile uint8_t *dwc_regs_base; volatile uint8_t *dwc_regs_base;
bool fiq_split_schedule_enable; /* false when we're terminating fiq_split_enable */
#else #else
volatile void *dwc_regs_base; volatile void *dwc_regs_base;
#endif #endif
...@@ -257,7 +258,11 @@ int notrace fiq_hcintr_handle(int channel, hfnum_data_t hfnum) ...@@ -257,7 +258,11 @@ int notrace fiq_hcintr_handle(int channel, hfnum_data_t hfnum)
int i; int i;
// Do not complete isochronous out transactions // Do not complete isochronous out transactions
#ifdef __riscos
if((hcchar.b.eptype == 1 && hcchar.b.epdir == 0) || !fiq_split_schedule_enable)
#else
if(hcchar.b.eptype == 1 && hcchar.b.epdir == 0) if(hcchar.b.eptype == 1 && hcchar.b.epdir == 0)
#endif
{ {
queued_port[channel] = 0; queued_port[channel] = 0;
fiq_print(FIQDBG_SCHED, "ISOC_OUT"); fiq_print(FIQDBG_SCHED, "ISOC_OUT");
......
...@@ -82,7 +82,6 @@ typedef struct dwc_softc { ...@@ -82,7 +82,6 @@ typedef struct dwc_softc {
#define DWC_SOFTC_INTR_ENDPT 1 #define DWC_SOFTC_INTR_ENDPT 1
extern bool use_fiq_fix;
extern bool reclaim_fiq_vector; extern bool reclaim_fiq_vector;
extern bool own_fiq_vector; extern bool own_fiq_vector;
......
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