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Commit 10052c0c authored by Jeffrey Lee's avatar Jeffrey Lee

Update to 'FIQ FSM' USB driver

Detail:
  Makefile, dwc/* - Updated to latest-ish code from Raspberry Pi github (rev c8baa9702c). Includes the 'FIQ FSM' USB driver, which replaces the older 'FIQ fix'. Note that many files appear to have no functional changes - just trailing whitespace removal to keep things in sync with github.
  Makefile - add DEBUGLIBS back into the debug libs listing to fix debug builds
  c/cmodule - Update to work with new FIQ FSM flags
  c/dwc_otg_riscos - Update to work with new FIQ FSM flags. Update initialisation procedure. Change IRQ handling to try both the HCD & CIL interrupt handlers (HCD can claim interrupt is handled when there's still a CIL interrupt pending). Disable support for falling back to IRQ if the FIQ vector is claimed by someone else - will need new implementation to cope with starting & stopping the FIQ FSM.
  s/regaccess - Update FIQ veneer & install routine to allow operation with either the dwc_otg_fiq_fsm or dwc_otg_fiq_nop functions.
Admin:
  Tested on Raspberry Pi 1 & 2


Version 0.21. Tagged as 'DWCDriver-0_21'
parent 88a7fa72
......@@ -33,7 +33,7 @@ DEBUG ?= FALSE
ifeq (${DEBUG},TRUE)
CFLAGS += -DDEBUGLIB -DDWCDRIVER_DEBUG -DDEBUG -DUSB_DEBUG
CMHGDEFINES += -DDWCDRIVER_DEBUG
LIBS += ${NET5LIBS}
LIBS += ${DEBUGLIBS} ${NET5LIBS}
endif
CFLAGS += -wp -wc
......@@ -47,8 +47,8 @@ VPATH = dwc.driver dwc.dwc_common_port
# DWC bits
CFLAGS += -DDWC_EN_ISOC -Idwc.dwc_common_port -DDWC_HOST_ONLY
CFLAGS += -Dnotrace=
OBJS += dwc_otg_cil dwc_otg_cil_intr dwc_otg_hcd dwc_otg_hcd_intr dwc_otg_hcd_queue dwc_otg_hcd_ddma dwc_otg_adp
CFLAGS += -Dnotrace= -Dnoinline=
OBJS += dwc_otg_cil dwc_otg_cil_intr dwc_otg_hcd dwc_otg_hcd_intr dwc_otg_hcd_queue dwc_otg_hcd_ddma dwc_otg_adp dwc_otg_fiq_fsm
# OBJS += dwc_cc dwc_modpow dwc_notifier dwc_mem
# Use this flag to enable Broadcom SoC/BCM2835-specific changes
......
/* (0.20)
/* (0.21)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.20
#define Module_MajorVersion_CMHG 0.21
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 21 Aug 2015
#define Module_Date_CMHG 07 Oct 2015
#define Module_MajorVersion "0.20"
#define Module_Version 20
#define Module_MajorVersion "0.21"
#define Module_Version 21
#define Module_MinorVersion ""
#define Module_Date "21 Aug 2015"
#define Module_Date "07 Oct 2015"
#define Module_ApplicationDate "21-Aug-15"
#define Module_ApplicationDate "07-Oct-15"
#define Module_ComponentName "DWCDriver"
#define Module_ComponentPath "mixed/RiscOS/Sources/HWSupport/USB/Controllers/DWCDriver"
#define Module_FullVersion "0.20"
#define Module_HelpVersion "0.20 (21 Aug 2015)"
#define Module_LibraryVersionInfo "0:20"
#define Module_FullVersion "0.21"
#define Module_HelpVersion "0.21 (07 Oct 2015)"
#define Module_LibraryVersionInfo "0:21"
......@@ -48,7 +48,7 @@
#include "dwc/driver/dwc_otg_hcd_if.h"
#include "dwc/driver/dwc_otg_regs.h"
#include "dwc/driver/dwc_otg_mphi_fix.h"
#include "dwc/driver/dwc_otg_fiq_fsm.h"
/*****************************************************************************
* Function prototypes - Private to this file
......@@ -83,9 +83,6 @@ int dwcdebug; /* Debug level */
#endif
bool microframe_schedule = true;
bool nak_holdoff_enable = true;
bool fiq_fix_enable = false;
bool fiq_split_enable = false;
extern int * init_veneer (void);
......@@ -440,7 +437,7 @@ int usb_irq_handler(_kernel_swi_regs *r, void *pw)
int ret;
#ifdef RISCOS_FIQ_DOWNGRADE
if(fiq_fix_enable)
if(fiq_enable)
{
/* Flag to the FIQ routine that we want the IRQ to be off */
fiq_downgrade.irq_masked = true;
......@@ -453,7 +450,7 @@ int usb_irq_handler(_kernel_swi_regs *r, void *pw)
ret = dwc_otg_riscos_irq(&dwc_soft);
#ifdef RISCOS_FIQ_DOWNGRADE
if(fiq_fix_enable)
if(fiq_enable)
{
/* Flag to the FIQ routine that it can enable the IRQ again */
fiq_downgrade.irq_masked = false;
......
......@@ -52,7 +52,7 @@
#include "dwc/driver/dwc_otg_dbg.h"
#include "dwc/driver/dwc_otg_driver.h"
#include "dwc/driver/dwc_otg_regs.h"
#include "dwc/driver/dwc_otg_mphi_fix.h"
#include "dwc/driver/dwc_otg_fiq_fsm.h"
/* CIL & HCD interface for RISC OS */
......@@ -104,22 +104,25 @@ struct dwc_otg_driver_module_params {
};
static const bool use_fiq_fix = true; /* True if we're allowed to use the FIQ fix */
static const bool use_fiq_split_fix = true; /* True if we're allowed to use the FIQ split xfer fix */
static const bool use_fiq_fsm = true; /* True if we're allowed to use the full FIQ FSM */
bool reclaim_fiq_vector = false; /* True if we should attempt to claim FIQs (i.e. driver is initialised and use_fiq_fix) */
bool own_fiq_vector = false; /* True if we currently own the FIQ vector */
extern bool fiq_fix_enable,fiq_split_enable,fiq_split_schedule_enable;
extern volatile uint8_t *dwc_regs_base;
extern mphi_regs_t c_mphi_regs;
extern void *dummy_send;
extern int complete_sched[MAX_EPS_CHANNELS];
static uint32_t fiq_stack[512];
/* Support for downgrading to IRQ when FIQ is claimed by someone else is incomplete */
//#define DOWNGRADE_TO_IRQ
#ifdef RISCOS_FIQ_DOWNGRADE
fiq_downgrade_t fiq_downgrade;
#endif
bool fiq_enable = false;
bool fiq_fsm_enable = false;
uint16_t nak_holdoff = 8;
unsigned short fiq_fsm_mask = 0x07;
/*
Misc
......@@ -518,6 +521,12 @@ _kernel_oserror *dwc_otg_riscos_init(const uint32_t *hw_base,const uint8_t *mphi
softc->mphi_device_number = mphi_device_number;
SIMPLEQ_INIT(&softc->sc_free_xfers);
#ifndef FALLBACK_TO_IRQ
/* FIQ FSM enable flags must be set to correct values prior to init */
fiq_enable = use_fiq_fix;
fiq_fsm_enable = use_fiq_fsm;
#endif
/* Initialise the common interface layer */
dprintf(("","dwc_otg_cil_init\n"));
softc->dwc_dev.core_if = dwc_otg_cil_init(hw_base);
......@@ -592,40 +601,23 @@ _kernel_oserror *dwc_otg_riscos_init(const uint32_t *hw_base,const uint8_t *mphi
return (_kernel_oserror *) "\0\0\0\0Incorrect device parameters";
}
/* Set up variables needed by the FIQ code */
dprintf(("","Registers at %08x %08x\n",hw_base,mphi_base));
dwc_regs_base = (volatile uint8_t *) hw_base;
c_mphi_regs.base = (volatile void *) (mphi_base);
c_mphi_regs.ctrl = (volatile void *) (mphi_base + 0x4c);
c_mphi_regs.outdda = (volatile void *) (mphi_base + 0x28);
c_mphi_regs.outddb = (volatile void *) (mphi_base + 0x2c);
c_mphi_regs.intstat = (volatile void *) (mphi_base + 0x50);
dummy_send = malloc(16);
/* Enable MPHI peripheral */
DWC_WRITE_REG32(c_mphi_regs.ctrl,0x80000000);
#ifdef RISCOS_FIQ_DOWNGRADE
fiq_downgrade.fiq_downgrade_device = mphi_device_number;
/* Get the MPHI generating an interrupt now */
FIQ_WRITE( c_mphi_regs.outdda, (int) dummy_send);
FIQ_WRITE( c_mphi_regs.outddb, (1 << 29));
_swix(OS_Hardware,_INR(8,9)|_OUTR(0,1),1,EntryNo_HAL_IRQEnable,&fiq_downgrade.hal_irqenable,&fiq_downgrade.hal_sb);
_swix(OS_Hardware,_INR(8,9)|_OUT(0),1,EntryNo_HAL_IRQDisable,&fiq_downgrade.hal_irqdisable);
#endif
/* Disable global interrupts */
dprintf(("","Setting up IRQs\n"));
dwc_otg_disable_global_interrupts(softc->dwc_dev.core_if);
/* Claim IRQ */
_swix (OS_ClaimDeviceVector, _INR(0,4), softc->usb_device_number, usb_irq_entry, private_word, 0, 0);
_swix (OS_Hardware, _IN(0) | _INR(8,9), softc->usb_device_number, 0, EntryNo_HAL_IRQEnable);
/* Try using FIQs */
dwc_otg_riscos_try_use_fiqs(softc,true);
#ifndef FALLBACK_TO_IRQ
if (use_fiq_fix)
{
_swix (OS_ClaimDeviceVector, _INR(0,4), softc->mphi_device_number, usb_irq_entry, private_word, 0, 0);
softc->device_number = softc->mphi_device_number;
}
else
#endif
{
_swix (OS_ClaimDeviceVector, _INR(0,4), softc->usb_device_number, usb_irq_entry, private_word, 0, 0);
_swix (OS_Hardware, _IN(0) | _INR(8,9), softc->usb_device_number, 0, EntryNo_HAL_IRQEnable);
}
/* Initialise CIL */
dprintf(("","dwc_otg_core_init\n"));
......@@ -647,6 +639,32 @@ _kernel_oserror *dwc_otg_riscos_init(const uint32_t *hw_base,const uint8_t *mphi
/* Get port number */
softc->port = dwc_otg_hcd_otg_port(softc->dwc_dev.hcd);
/* Set up variables needed by the FIQ code */
dprintf(("","Registers at %08x %08x\n",hw_base,mphi_base));
if (use_fiq_fix)
{
softc->dwc_dev.hcd->fiq_state->mphi_regs.base = (volatile void *) (mphi_base);
softc->dwc_dev.hcd->fiq_state->mphi_regs.ctrl = (volatile void *) (mphi_base + 0x4c);
softc->dwc_dev.hcd->fiq_state->mphi_regs.outdda = (volatile void *) (mphi_base + 0x28);
softc->dwc_dev.hcd->fiq_state->mphi_regs.outddb = (volatile void *) (mphi_base + 0x2c);
softc->dwc_dev.hcd->fiq_state->mphi_regs.intstat = (volatile void *) (mphi_base + 0x50);
softc->dwc_dev.hcd->fiq_state->dwc_regs_base = (uint8_t *) hw_base;
/* Enable MPHI peripheral */
DWC_WRITE_REG32(softc->dwc_dev.hcd->fiq_state->mphi_regs.ctrl,0x80000000);
#ifdef RISCOS_FIQ_DOWNGRADE
fiq_downgrade.fiq_downgrade_device = mphi_device_number;
/* Get the MPHI generating an interrupt now */
FIQ_WRITE( softc->dwc_dev.hcd->fiq_state->mphi_regs.outdda, (int) softc->dwc_dev.hcd->fiq_state->dummy_send);
FIQ_WRITE( softc->dwc_dev.hcd->fiq_state->mphi_regs.outddb, (1 << 29));
_swix(OS_Hardware,_INR(8,9)|_OUTR(0,1),1,EntryNo_HAL_IRQEnable,&fiq_downgrade.hal_irqenable,&fiq_downgrade.hal_sb);
_swix(OS_Hardware,_INR(8,9)|_OUT(0),1,EntryNo_HAL_IRQDisable,&fiq_downgrade.hal_irqdisable);
#endif
}
/* Enable IRQs */
dprintf(("","dwc_otg_enable_global_interrupts\n"));
dwc_otg_enable_global_interrupts(softc->dwc_dev.core_if);
......@@ -661,6 +679,12 @@ _kernel_oserror *dwc_otg_riscos_init(const uint32_t *hw_base,const uint8_t *mphi
return (_kernel_oserror *) "\0\0\0\0Failed to start HCD";
}
if (use_fiq_fix)
{
/* Try using FIQs - must occur after hcd_start to avoid issues with FIQ FSM generating HCD IRQs before hcd_intr is able to deal with them */
dwc_otg_riscos_try_use_fiqs(softc,true);
}
/* We don't get any notification from the DWC layer when the root hub status changes. For now, just use a ticker event that will poll the driver at regular intervals. */
callx_add_callevery(10,softc_root_intr_ticker,softc);
......@@ -685,12 +709,6 @@ void dwc_otg_riscos_shutdown(dwc_softc_t *softc)
softc->dwc_dev.hcd = NULL;
}
if(softc->dwc_dev.core_if)
{
dwc_otg_cil_remove(softc->dwc_dev.core_if);
softc->dwc_dev.core_if = NULL;
}
/* Release FIQ */
if(own_fiq_vector)
{
......@@ -699,14 +717,15 @@ void dwc_otg_riscos_shutdown(dwc_softc_t *softc)
dwc_otg_riscos_release_fiq(softc);
_swix(OS_ServiceCall,_IN(1),Service_ReleaseFIQ);
}
if(dummy_send)
{
free(dummy_send);
dummy_send = NULL;
}
/* Release IRQ */
_swix (OS_ReleaseDeviceVector, _INR(0,4), softc->usb_device_number, usb_irq_entry, private_word, 0, 0);
_swix (OS_ReleaseDeviceVector, _INR(0,4), softc->device_number, usb_irq_entry, private_word, 0, 0);
if(softc->dwc_dev.core_if)
{
dwc_otg_cil_remove(softc->dwc_dev.core_if);
softc->dwc_dev.core_if = NULL;
}
/* Free remaining memory */
usbd_xfer_handle xfer;
......@@ -720,26 +739,26 @@ void dwc_otg_riscos_shutdown(dwc_softc_t *softc)
int dwc_otg_riscos_irq(dwc_softc_t *softc)
{
/* Return 0 for success, 1 for failure */
int ret;
int ret = 0;
if(softc->hcd_on)
{
/* Check HCD interrupt first, likely to be more common */
ret = dwc_otg_hcd_handle_intr(softc->dwc_dev.hcd);
if(ret)
return 0;
}
/* Check CIL */
ret = dwc_otg_handle_common_intr(&softc->dwc_dev);
ret |= dwc_otg_handle_common_intr(&softc->dwc_dev);
if(ret)
{
return 0;
}
/* Unhandled (spurious?) IRQs may happen every so often when using the FIQ fix. Try not to worry about it! */
return (use_fiq_fix?0:1);
}
extern void install_fiq(uint32_t *stack,uint32_t stacksize);
extern void install_fiq(uint32_t *stack,uint32_t stacksize,void *param1,int param2,void *func);
void dwc_otg_riscos_try_use_fiqs(dwc_softc_t *softc, bool need_to_claim)
{
......@@ -761,17 +780,19 @@ void dwc_otg_riscos_try_use_fiqs(dwc_softc_t *softc, bool need_to_claim)
_swix (OS_Hardware, _INR(8,9), 0, EntryNo_HAL_FIQDisableAll);
/* Install FIQ handler */
install_fiq(fiq_stack,sizeof(fiq_stack));
install_fiq(fiq_stack,sizeof(fiq_stack),softc->dwc_dev.hcd->fiq_state,softc->dwc_dev.core_if->core_params->host_channels,(use_fiq_fsm?(void *)dwc_otg_fiq_fsm:(void *)dwc_otg_fiq_nop));
/* Disable IRQs+FIQs while we switch state */
int flags;
local_irq_save(flags);
local_fiq_disable();
#ifdef FALLBACK_TO_IRQ
/* Switch the IRQ handler from USB to MPHI */
_swix (OS_ReleaseDeviceVector, _INR(0,4), softc->usb_device_number, usb_irq_entry, private_word, 0, 0);
_swix (OS_ClaimDeviceVector, _INR(0,4), softc->mphi_device_number, usb_irq_entry, private_word, 0, 0);
softc->device_number = softc->mphi_device_number;
#endif
#if defined(RISCOS_FIQ_DOWNGRADE)
/* Ensure the FIQ routine will enable the interrupt */
......@@ -786,10 +807,10 @@ void dwc_otg_riscos_try_use_fiqs(dwc_softc_t *softc, bool need_to_claim)
_swix (OS_Hardware, _IN(0) | _INR(8,9), softc->usb_device_number, 0, EntryNo_HAL_FIQEnable);
/* Flag to DWC that the FIQ code is enabled */
fiq_fix_enable = use_fiq_fix;
fiq_enable = use_fiq_fix;
/* Also enable the split xfer fix */
fiq_split_enable = fiq_split_schedule_enable = use_fiq_split_fix;
/* Also enable the fiq FSM */
fiq_fsm_enable = use_fiq_fsm;
/* Flag that we own the vector, and should reclaim it if we lose it */
own_fiq_vector = reclaim_fiq_vector = true;
......@@ -803,20 +824,9 @@ void dwc_otg_riscos_release_fiq(dwc_softc_t *softc)
int flags;
/* If the split FIQ fix is enabled then we must do a staged release to
allow it to gracefully terminate its state machine */
if(fiq_split_enable)
{
/* Prevent new split xfers from being scheduled for completion by the FIQ handler. The IRQ handler will handle them instead. */
fiq_split_schedule_enable = false;
/* Wait for existing xfers to leave the FIQ schedule */
for(int i=0;i<MAX_EPS_CHANNELS;i++)
while(complete_sched[i] != -1)
{
dprintf(("","Waiting for complete_sched[%d]...\n",i));
}
dprintf(("","complete_sched is clear\n"));
}
#ifdef FALLBACK_TO_IRQ
TODO: Shutdown FIQ FSM
#endif
/* Release our claim on the FIQ vector */
local_irq_save(flags);
......@@ -825,12 +835,10 @@ void dwc_otg_riscos_release_fiq(dwc_softc_t *softc)
/* Disable the interrupt */
_swix (OS_Hardware, _INR(8,9), 0, EntryNo_HAL_FIQDisableAll);
/* Flag to DWC that the FIQ code is no longer active */
fiq_fix_enable = fiq_split_enable = false;
/* Flag that we no longer own the vector */
own_fiq_vector = false;
#ifdef FALLBACK_TO_IRQ
/* Switch the IRQ handler from MPHI to USB */
_swix (OS_ReleaseDeviceVector, _INR(0,4), softc->mphi_device_number, usb_irq_entry, private_word, 0, 0);
_swix (OS_ClaimDeviceVector, _INR(0,4), softc->usb_device_number, usb_irq_entry, private_word, 0, 0);
......@@ -838,6 +846,7 @@ void dwc_otg_riscos_release_fiq(dwc_softc_t *softc)
/* Enable USB IRQ */
_swix (OS_Hardware, _IN(0) | _INR(8,9), softc->usb_device_number, 0, EntryNo_HAL_IRQEnable);
#endif
local_irq_restore(flags);
}
/*
* dwc_otg_fiq_fsm.S - assembly stub for the FSM FIQ
*
* Copyright (c) 2013 Raspberry Pi Foundation
*
* Author: Jonathan Bell <jonathan@raspberrypi.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Raspberry Pi nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <asm/assembler.h>
#include <linux/linkage.h>
.text
.global _dwc_otg_fiq_stub_end;
/**
* _dwc_otg_fiq_stub() - entry copied to the FIQ vector page to allow
* a C-style function call with arguments from the FIQ banked registers.
* r0 = &hcd->fiq_state
* r1 = &hcd->num_channels
* r2 = &hcd->dma_buffers
* Tramples: r0, r1, r2, r4, fp, ip
*/
ENTRY(_dwc_otg_fiq_stub)
/* Stash unbanked regs - SP will have been set up for us */
mov ip, sp;
stmdb sp!, {r0-r12, lr};
#ifdef FIQ_DEBUG
// Cycle profiling - read cycle counter at start
mrc p15, 0, r5, c15, c12, 1;
#endif
/* r11 = fp, don't trample it */
mov r4, fp;
/* set EABI frame size */
sub fp, ip, #512;
/* for fiq NOP mode - just need state */
mov r0, r8;
/* r9 = num_channels */
mov r1, r9;
/* r10 = struct *dma_bufs */
// mov r2, r10;
/* r4 = &fiq_c_function */
blx r4;
#ifdef FIQ_DEBUG
mrc p15, 0, r4, c15, c12, 1;
subs r5, r5, r4;
// r5 is now the cycle count time for executing the FIQ. Store it somewhere?
#endif
ldmia sp!, {r0-r12, lr};
subs pc, lr, #4;
_dwc_otg_fiq_stub_end:
END(_dwc_otg_fiq_stub)
......@@ -162,7 +162,7 @@ fail:
/**
* usb_gadget_get_string - fill out a string descriptor
* usb_gadget_get_string - fill out a string descriptor
* @table: of c strings encoded using UTF-8
* @id: string id, from low byte of wValue in get string descriptor
* @buf: at least 256 bytes
......@@ -284,7 +284,7 @@ int usb_gadget_config_buf(
/* config descriptor first */
if (length < USB_DT_CONFIG_SIZE || !desc)
return -EINVAL;
*cp = *config;
*cp = *config;
/* then interface/endpoint/class/vendor/... */
len = usb_descriptor_fillbuf(USB_DT_CONFIG_SIZE + (u8*)buf,
......@@ -596,7 +596,7 @@ static const struct usb_cs_as_general_descriptor
z_audio_cs_as_if_desc = {
.bLength = 7,
.bDescriptorType = 0x24,
.bDescriptorSubType = 0x01,
.bTerminalLink = 0x01,
.bDelay = 0x0,
......@@ -604,11 +604,11 @@ z_audio_cs_as_if_desc = {
};
static const struct usb_cs_as_format_descriptor
static const struct usb_cs_as_format_descriptor
z_audio_cs_as_format_desc = {
.bLength = 0xe,
.bDescriptorType = 0x24,
.bDescriptorSubType = 2,
.bFormatType = 1,
.bNrChannels = 1,
......@@ -619,7 +619,7 @@ z_audio_cs_as_format_desc = {
.tUpperSamFreq = {0xe2, 0xd6, 0x00},
};
static const struct usb_endpoint_descriptor
static const struct usb_endpoint_descriptor
z_iso_ep = {
.bLength = 0x09,
.bDescriptorType = 0x05,
......@@ -628,31 +628,31 @@ z_iso_ep = {
.wMaxPacketSize = 0x0038,
.bInterval = 0x01,
.bRefresh = 0x00,
.bSynchAddress = 0x00,
.bSynchAddress = 0x00,
};
static char z_iso_ep2[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
// 9 bytes
static char z_ac_interface_header_desc[] =
static char z_ac_interface_header_desc[] =
{ 0x09, 0x24, 0x01, 0x00, 0x01, 0x2b, 0x00, 0x01, 0x01 };
// 12 bytes
static char z_0[] = {0x0c, 0x24, 0x02, 0x01, 0x01, 0x01, 0x00, 0x02,
static char z_0[] = {0x0c, 0x24, 0x02, 0x01, 0x01, 0x01, 0x00, 0x02,
0x03, 0x00, 0x00, 0x00};
// 13 bytes
static char z_1[] = {0x0d, 0x24, 0x06, 0x02, 0x01, 0x02, 0x15, 0x00,
static char z_1[] = {0x0d, 0x24, 0x06, 0x02, 0x01, 0x02, 0x15, 0x00,
0x02, 0x00, 0x02, 0x00, 0x00};
// 9 bytes
static char z_2[] = {0x09, 0x24, 0x03, 0x03, 0x01, 0x03, 0x00, 0x02,
static char z_2[] = {0x09, 0x24, 0x03, 0x03, 0x01, 0x03, 0x00, 0x02,
0x00};
static char za_0[] = {0x09, 0x04, 0x01, 0x02, 0x01, 0x01, 0x02, 0x00,
static char za_0[] = {0x09, 0x04, 0x01, 0x02, 0x01, 0x01, 0x02, 0x00,
0x00};
static char za_1[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
static char za_2[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x01, 0x08, 0x00,
static char za_2[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x01, 0x08, 0x00,
0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
static char za_3[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00,
......@@ -686,12 +686,12 @@ static char za_13[] = {0x09, 0x05, 0x04, 0x09, 0xe0, 0x00, 0x01, 0x00,
static char za_14[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
static char za_15[] = {0x09, 0x04, 0x01, 0x05, 0x01, 0x01, 0x02, 0x00,
static char za_15[] = {0x09, 0x04, 0x01, 0x05, 0x01, 0x01, 0x02, 0x00,
0x00};
static char za_16[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
static char za_17[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x03, 0x14, 0x00,
static char za_17[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x03, 0x14, 0x00,
0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
static char za_18[] = {0x09, 0x05, 0x04, 0x09, 0xa8, 0x00, 0x01, 0x00,
......@@ -704,7 +704,7 @@ static char za_20[] = {0x09, 0x04, 0x01, 0x06, 0x01, 0x01, 0x02, 0x00,
static char za_21[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
static char za_22[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x03, 0x14, 0x00,
static char za_22[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x03, 0x14, 0x00,
0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
static char za_23[] = {0x09, 0x05, 0x04, 0x09, 0x50, 0x01, 0x01, 0x00,
......@@ -806,7 +806,7 @@ config_buf (struct usb_gadget *gadget, u8 *buf, u8 type, unsigned index)
{
int len;
const struct usb_descriptor_header **function;
function = z_function;
len = usb_gadget_config_buf (&z_config, buf, USB_BUFSIZ, function);
if (len < 0)
......@@ -906,7 +906,7 @@ static void zero_reset_config (struct zero_dev *dev)
#define _write(f, buf, sz) (f->f_op->write(f, buf, sz, &f->f_pos))
static void
static void
zero_isoc_complete (struct usb_ep *ep, struct usb_request *req)
{
struct zero_dev *dev = ep->driver_data;
......@@ -1253,7 +1253,7 @@ zero_setup (struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
case 0x0300:
((u8*)req->buf)[0] = 0x60;
break;
case 0x0500:
case 0x0500:
((u8*)req->buf)[0] = 0x18;
break;
}
......@@ -1283,7 +1283,7 @@ zero_setup (struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
value = ctrl->wLength;
break;
default:
unknown:
printk("unknown control req%02x.%02x v%04x i%04x l%d\n",
......@@ -1521,7 +1521,7 @@ static int isoc_read_data (char *page, char **start,
page[i] = rbuf[(c+s) % RBUF_LEN];
}
*start = page;
if (c >= rbuf_len) {
*eof = 1;
done = 1;
......@@ -1568,7 +1568,7 @@ static void __exit cleanup (void)
{
usb_gadget_unregister_driver (&zero_driver);
remove_proc_entry("isoc_data", pdir);
remove_proc_entry("isoc_test", NULL);
}
......
......@@ -88,7 +88,7 @@ uint32_t dwc_otg_adp_read_reg_filter(dwc_otg_core_if_t * core_if)
adpctl.b.adp_tmout_int = 0;
adpctl.b.adp_prb_int = 0;
adpctl.b.adp_tmout_int = 0;
return adpctl.d32;
}
......@@ -179,7 +179,7 @@ static void adp_vbuson_timeout(void *ptr)
}