; Copyright 2003 Tematic Ltd ; ; Licensed under the Apache License, Version 2.0 (the "License"); ; you may not use this file except in compliance with the License. ; You may obtain a copy of the License at ; ; http://www.apache.org/licenses/LICENSE-2.0 ; ; Unless required by applicable law or agreed to in writing, software ; distributed under the License is distributed on an "AS IS" BASIS, ; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ; See the License for the specific language governing permissions and ; limitations under the License. ; ;------------------------------------------------------------------------------ ; ; defaultHostID EQU 7 maxDeviceID EQU 7 ;Host/Target DeviceID's are 0..7 minCDBLen EQU 3 ;Imposed by LoadCDBregisters maxCDBLen EQU 12 ;SBIC has 12 CDB registers DeviceIDMask EQU 7 DeviceIDShft EQU 0 CardIDMask EQU &18 CardIDShft EQU 3 LUNIDMask EQU &E0 LUNIDShft EQU 5 Log2PAGESIZE EQU 12 PAGESIZE EQU 4096 ;SRAM is 64K in 16 x 4K pages PAGECOUNT EQU 16 PANICPAGE EQU 0 ;Page 0 used to sink/source unwanted data PAGEBITS EQU &0000FFFE ;Pages 1..15, initially marked as unallocated ;Pages 16..31 don't exist, marked as allocated ASSERT (PAGESIZE = (1 :SHL: Log2PAGESIZE)) CMDCOUNT EQU 16 ;Number of queued commands CMDBITS EQU &0000FFFF ; ASSERT (CMDBITS = (1 :SHL: CMDCOUNT)-1) UnixAccessKey EQU &FC000003 ;Magic value that allows UNIX to break the ; AccessKey system. ONLY allowed on SWI SCSI_Op ; If the user of this key corrupts your DISC ; DON'T COME CRYING TO ME. RCsoftcopyadr * &9A LF * 10 CR * 13 SPACE * 32 EscapeBit EQU &40 ;This bit indicates escape pressed IDLE EQU &00000000 RUNNING EQU &00000004 STALLED EQU &00000008 WAITING EQU &00000010 INITIALISING EQU &00000020 INITIALISED EQU &00000040 ERROR EQU &00000080 ;------------------------------------------------------------------------------ ; ; Register names ; ============== ; rPAGESLOTptr RN 7 rCMDptr RN 8 rDEVICEptr RN 9 rPODULEptr RN 10 rDMACptr RN 11 ;WsPtr RN 12 StkPtr RN 13 Link RN 14 ;PC RN 15 ;------------------------------------------------------------------------------ ; ; Access to stacked registers - TO BE USED WITH CAUTION! ; =========================== ^ 0,StkPtr StackedR0 # 4 StackedR1 # 4 StackedR2 # 4 StackedR3 # 4 StackedR4 # 4 StackedR5 # 4 StackedR6 # 4 StackedR7 # 4 ;============================================================================== ; ; ; ; Podule SRAMptr DMACptr PODULEptr ; 0 03240000 03000000 03003000 03343000 ; 1 03244000 ; 2 03248000 ; 3 0324C000 ; Podule0SlowAccess EQU &03240000 PoduleSpeedMask EQU &00180000 SRAMptrRel EQU &03000000 - Podule0SlowAccess DMACptrRel EQU &03003000 - Podule0SlowAccess PODULEptrRel EQU &03343000 - Podule0SlowAccess ;============================================================================== ; ; Podule registers ; ;------------------------------------------------------------------------------ ; ; Both memory mapped, accessed by +ve/-ve offsets off rPODULEptr (R10) ; ^ -4,rPODULEptr PR_IntStat # 0 ;Read : Interrupt status PR_ClrInt # 4 ;Write: Clear DMAC interrupt PR_PageReg # 0 ;Write: PageRegister/IntEnable/UserReset Pod_IRQ EQU &01 ;Podule IRQ (Set if TC_IRQ or SB_IRQ) TC_IRQ EQU &02 ; DMAC terminal count SB_IRQ EQU &08 ; SBIC interrupting Pod_EnableInts EQU &40 Pod_ForceReset EQU &80 ; ; ;============================================================================== ;============================================================================== ; ; SBIC registers, commands and status bits ; ;---------------------------------------------------------------------------- ; ; SBIC registers ; ^ -8,rDMACptr ; bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SBICauxstat # 0 ; RO INT LCI BSY CIP 0 0 PE DBR SBICaddress # 4 ; WO Register selection address SBICindirect # 4 ; Read/write register given by address register ; ; Register indicators, must be written to SBIC address register (see wrSBIC ; & rdSBIC macros) ; ; bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SR_OwnID EQU &00 ; RW FS1 FS0 0 EHP EAF ID2 ID1 ID0 SR_Control EQU &01 ; RW DM2 DM1 DM0 HHP EDI IDI HA HSP SR_Timeout EQU &02 ; RW timeout period value = Tper*Ficlk/80d SR_CDB EQU &03 SR_TargetLUN EQU &0F ; RW TLV DOK 0 0 0 TL2 TL1 TL0 SR_Phase EQU &10 SR_SyncXfer EQU &11 SR_CountHi EQU &12 ; RW Transfer count MSB SR_CountMd EQU &13 SR_CountLo EQU &14 ; RW Transfer count LSB SR_DestID EQU &15 ; SCC DPD 0 0 0 DI2 DI1 DI0 SR_SourceID EQU &16 ; RW ER ES DSP 0 SIV SI2 SI1 SI0 SR_SCSIstat EQU &17 SR_Command EQU &18 SR_Data EQU &19 ; ; ;------------------------------------------------------------------------------ ; ; SBIC commands - Actioned by writing to SBIC command register (SR_Command) ; SC_Reset EQU &00 ; Level 1 SC_Abort EQU &01 ; 1 SC_AssertATN EQU &02 ; 1 SC_NegateACK EQU &03 ; 1 SC_Disconnect EQU &04 ; 1 SC_Sel_withATN EQU &06 ; Level 2 SC_Sel_Tx_withATN EQU &08 ; 2 SC_Sel_Tx_woATN EQU &09 ; 2 SC_SetIDI EQU &0F ; 2 SC_Transfer_Info EQU &20 ; 2 SC_Transfer_Info_SBT EQU &A0 ; 2 ; ; ;------------------------------------------------------------------------------ ; ; Host status - Indicates cause of most recent SBIC interrupt, read from SCSI ; status register (SR_SCSIstat) ; ; Format: 1 byte: iiiiqqqq (1=interrupt type bits, q=qualifier bits) ; HOST_Type_Mask EQU 2_11110000 ;Mask to extract interrupt type ; HOST_RESET EQU 2_00000001 ;Reset - advanced features enabled HOST_COMPLETE EQU 2_00010000 HOST_PAUSED EQU 2_00100000 HOST_TERMINATED EQU 2_01000000 HOST_SERVICE EQU 2_10000000 ; HOST_Qualifier_Mask EQU 2_00001111 ;Mask to extract qualifier ; HOST_TIMEOUT EQU 2_01000010 ; ; ;------------------------------------------------------------------------------ ; ; SBIC general status bits - Read from SBIC auxiliary status register ; (SBIXauxstat) ; DBR EQU &01 ;Data Buffer Ready PE EQU &02 ;Parity Error CIP EQU &10 ;Command In Progress BSY EQU &20 ;BuSY - Level II command executing LCI EQU &40 ;Last Command Ignored INT EQU &80 ;INTerrupt pending ; ; ;------------------------------------------------------------------------------ ; Bits in SR_OwnID EAF EQU &08 ;Enable Advanced Features ;EHP EQU &10 ;Enable Host Parity ;---------------------- ; Bits in SR_Control IDI EQU &04 ;Intermediate Disconnect Interrupt ;EDI EQU &08 ;Ending Disconnect Interrupt DMAmode EQU &20 ;SBIC burst DMA mode ;----------------- ; Bits in SR_DestID DPD EQU &40 ;Data Phase Direction, set for DataIn expected ;---------------- ; Bits in SR_SourceID ER EQU &80 ;Enable reselection SIV EQU &08 ;Source ID valid ; ;---------------- ; SyncMode EQU &20 ;REQ/ACK pulse width of 1 cycle SelectTimeout EQU 10 ;SBIC 100mS timeout on select phase ; ; ;============================================================================== ;============================================================================== ; ; DMAC registers and control bits ; ;------------------------------------------------------------------------------ ; ; DMAC registers - memory mapped, accessed by +ve offsets off rDMACptr (R11) ; ^ 0,rDMACptr ;Offset DR_Initialise # &200 ; 000 DR_Channel # -&1FC ; 200 DR_TxCntLo # &200 ; 004 DR_TxCntHi # -&1FC ; 204 DR_TxAdrLo # &200 ; 008 DR_TxAdrMd # -&1FC ; 208 DR_TxAdrHi # &200 ; 00C DR_Unused # -&1FC ; 20C DR_DevCon1 # &200 ; 010 DR_DevCon2 # -&1FC ; 210 DR_ModeCon # &200 ; 014 DR_Status # -&1FC ; 214 DR_TempLo # &200 ; 018 DR_TempHi # -&1FC ; 218 DR_Request # &200 ; 01C DR_Mask # -&1FC ; 21C ; ; ;------------------------------------------------------------------------------ ; dmac_bits EQU &01 ;Active, 8bit mode ctrl1 EQU &60 ;Active low DRQ/DACK, extended write ctrl2 EQU &01 ;Bus hold between cycles clr_mask EQU &0E ;Channel 0 may interrupt set_mask EQU &0F ;Set all DRQ masks dma_rd_mode EQU &04 ;Demand mode, read dma_wr_mode EQU &08 ;Demand mode, write ; ; ;============================================================================== ;============================================================================== ; ; SCSI command, message and status bytes ; ;------------------------------------------------------------------------------ ; ; SCSI commands - Operation codes held in the 1st byte of a CDB (command ; descriptor block). ; C_INQUIRY EQU &12 INQUIRY_BLK_SIZE EQU 5 ;Used by 'Determine Device' INQUIRY_BLK_SIZEL EQU 36 Describe_BLK_SIZE EQU (INQUIRY_BLK_SIZEL + READCAPACITY_BLK_SIZE) C_READCAPACITY EQU &25 READCAPACITY_BLK_SIZE EQU 8 ;Used by 'Determine Device' Determine_BLK_SIZE EQU (INQUIRY_BLK_SIZE + READCAPACITY_BLK_SIZE) C_REQUESTSENSE EQU &03 REQUESTSENSE_BLK_SIZE EQU &08 ;Space for 8 bytes of extended sense ; ; ;------------------------------------------------------------------------------ ; ; SCSI Message codes - In = Target to initiator, Out = Initiator to Target ; MESSAGE_COMMANDCOMPLETE EQU &00 ; In MESSAGE_EXTENDEDMESSAGE EQU &01 ; In Out MESSAGE_SAVEDATAPOINTER EQU &02 ; In MESSAGE_RESTOREDATAPOINTER EQU &03 ; In MESSAGE_DISCONNECT EQU &04 ; In MESSAGE_ABORT EQU &06 ; Out MESSAGE_REJECT EQU &07 ; In Out MESSAGE_NOOPERATION EQU &08 ; Out MESSAGE_BUSDEVICERESET EQU &0C ; Out ; ; ;------------------------------------------------------------------------------ ; ; Target status - Returned by the Target during the status phase of command ; ; Format: 1 byte: rvvSSSSv (r=reserved, v=vendor unique, S=status bit) ; TARGET_Mask EQU 2_10011110 ;Mask to extract status bits ; TARGET_GOOD EQU 2_00000000 TARGET_CHECK_CONDITION EQU 2_00000010 TARGET_BUSY EQU 2_00001000 ; ; Pseudo target status values ; TARGET_TIMEOUT EQU &0100 ;Timeout during selection ;We sent MESSAGE_ABORT TARGET_TIMEOUT2 EQU &0200 ; cos operation took too long TARGET_ESCAPED EQU &0300 ; cos user pressed escape TARGET_ABORTOP EQU &0400 ; cos user did AbortOp TARGET_ABORTDEVICE EQU &0500 ; cos user did AbortDevice ;We sent MESSAGE_BUSDEVICERESET TARGET_RESET EQU &0600 ; cos user did ResetDevice TARGET_UNEXPECTEDDISCONNECT EQU &0700 ;Target dropped dead!!! ; ; ;============================================================================== ;============================================================================== ; ; Misc records - RamRec, PtrRec and CmdRec ; ;------------------------------------------------------------------------------ ; ; The SRAM is visible as 16 x 4K pages (PAGECOUNT x PAGELEN), ; Data transfer between MainRam & SRAM is by a fast data copier using LDM/STM ; in chunks of PAGELEN bytes or less. ; Data transfer between SRAM & SBIC uses the DMAC controler and is in chunks ; of PAGELEN bytes or less. ; ; For each slot, we maintain a record of the MainRam address,SRAMpage, ; SRAMoffset and Block size of a chunk. ; ; For each device, we maintain a circular queue indicating slots allocated to ; that device. ; ; Consider the READ case (Target->Host) ; The DMAC, if running, fills the slot whose number is held in DMACram. ; On completion of that chunk (terminal count interrupt), DMACram is ; queued. If there is further data to transfer and a page can be claimed ; to DMA it into, that page number is written into DMACram and the DMAC ; restarted, if not the DMAC status is set to IDLE or STALLED as appropriate. ; ; The copier will run for as long as QStart<>QEnd and will copy the page ; whose slot number appears at QStart. On completion of that page, QStart is ; advanced. When QStart=QEnd, the copier status is set to IDLE or STALLED ; as appropriate. ; ; The slots freed by the copier will allow a stalled DMAC to be restarted and ; slots filled by the DMAC may allow a stalled Copier to be restarted. ; ^ 0,rPAGESLOTptr RamTxAdr # 4 ;Main memory Src/Dst address RamBlkSz # 4 ;BlockSize RamOffset # 4 ;SRAM offset (0/1/2/3) RamPage # 4 ;SRAM page ; RamRecSize # 0 ; ; ;------------------------------------------------------------------------------ ; ; A SCSI pointer record, used by SavedPointers,CurrentPointers & FuturePointers ; ^ 0 ScatPtr # 4 EntAdr # 4 EntCnt # 4 TtlCnt # 4 ; PtrRecSize # 0 ; ; ;------------------------------------------------------------------------------ ; ; Commands are queued, and start executing in chronological order, ; if a device allows disconnection, it may disconnect, allowing a ; later command (for a different device) to be started. ; Although commands are started in order, they may complete and hence be ; removed from the queue in any order. ; ^ 0,rCMDptr CmdDevID # 4 ; } Copy of SCSIop CmdCDBLen # 4 ; } CmdCDB # 12 ;N.B. Copy of CDB } CmdXferPtr # 4 ; } CmdXferLen # 4 ; } parameters [ soft CmdCallbackR5 # 4 ; } | CmdTimeout # 4 ; } ] CmdCallbackAdr # 4 ; } CmdCallbackR12 # 4 ; } CmdRtR3 # 4 ; } CmdRtR4 # 4 ; } CmdStat # 4 ;Waiting/Initialising/Initialised/Running/Idle ;CmdCtl # 4 ;Send message/Execute CDB/Request sense CmdOpID # 4 ;Command ID returned to user CmdNxt # 4 ;Link to next command (chronological order) spare0 # 4 CmdRecSize # 0 Log2CMDRECSIZE EQU 6 ASSERT ((:INDEX: CmdRecSize) = (1 :SHL: Log2CMDRECSIZE)) ; ; ;============================================================================== ;============================================================================== ; ; Workspace for SCSI device ; ^ 0,rDEVICEptr DeviStat # 4 ;absent/idle/running CopyStat # 4 ; idle/running/stalled DMACStat # 4 ; idle/running/stalled SBICStat # 4 ; idle/running Connected # 4 ;0/~0 for disconnected/connected MessageIn # 4 ;Last message we received MessageOut # 4 ;Last message we managed to send TargStat # 4 ;Copied from SBIC TargetLUN register on ; completion of 'Select-And-Transfer' HostStat # 4 ;Copied from SBIC SCSI status register HostStat1 # 4 ;Previous value [ debug HostStat2 # 4 HostStat3 # 4 HostStat4 # 4 HostStat5 # 4 HostStat6 # 4 HostStat7 # 4 ] [ debug ;IntStat # 4 HostAuxStat # 4 ; ;HostPhase # 4 ] CpyCtl # 4 CpyAdr # 4 ;>>>not needed??? ;Main memory address to copy to/from CpyCnt # 4 ;Transfer size loaded into SBIC CpyFail # 4 ;Amount NOT transfered SavedPointers # 0 ;SavedPointers SavdScatPtr # 4 ; SavdEntAdr # 4 ; SavdEntCnt # 4 ; SavdTtlCnt # 4 ; see PtrRecSize CurrentPointers # 0 ;CurrentPointers CurrScatPtr # 4 ; ;Pointer to next Address/Length pair to use CurrEntAdr # 4 ; CurrEntCnt # 4 ; CurrTtlCnt # 4 ; see PtrRecSize FuturePointers # 0 ;FuturePointers FutrScatPtr # 4 ;Used only when writing, FutrEntAdr # 4 ; to allow data to be copied to SRAM FutrEntCnt # 4 ; before the DMAC needs it. FutrTtlCnt # 4 ; see PtrRecSize DemandSlot # :INDEX: RamRecSize Timeout # 4 QStart # 4 ; } Offsets to Queue0..Queue19 QEnd # 4 ; } Queue bigger than number of pages to Queue0 # (PAGECOUNT+4)*4 ; } prevent full/empty ambiguity QueuePastIt # 0 ; DMACram # 4 ;If reading, this is the RAM page (0..15), that ; the DMAC is filling. ;If writing, this is the RAM page the DMAC is ; emptying. CMDptr # 4 ;Pointer to current CmdRec FakeScatterAdr # 4 ;If user didn't supply a scatter list, dump FakeScatterLen # 4 ; address & len here and use this SenseBlk # REQUESTSENSE_BLK_SIZE ;Good place to put Sense Data if doing ; automatic Request sense on check condition PendingCnt # 4 ;Number of commands queued for this device SoftClearDevCBEnd # 0 ;Extent of clearing/initialise for 'soft' initialise [ :LNOT:soft ReleaseCallAdr # 4 ReleaseCallR12 # 4 AccessKey # 4 ControlTimeout # 4 ControlBits # 4 ] HoldCmd # 4 ;Used to hold SBIC state around MessageIN HoldPhase # 4 ; MessageOut phases HoldCount # 4 [ bugfix2 Suppress # 4 ;Bit mask of messages (out) to be suppressed ; normally zero, holds CTL_Suppress after ; MESSAGE_COMMANDCOMPLETE received ] HardClearDevCBEnd # 0 ;Extent of clearing/initialise for 'hard' initialise deviceRecSize # 0 ; ; ;============================================================================== ;============================================================================== ; ; Workspace for ONE SCSI card ; ^ 0,WsPtr DEVICEptr # 4 ;0 or ->DevCB(0..7) PODULEptr # 4 ;Typicaly &03343000 (for slot 0) DMACptr # 4 ;Typicaly &03003000 (for slot 0) SRAMptr # 4 ;Typicaly &03000000 (for slot 0) HostID # 4 ;0..7, typicaly 7 ClearWSStart # 0 OperationID # 4 ;Next operation ID to be issued Lockout # 4 QuadDump # 16 RamMap # 4 ;Bit vector of RAM pages in use Ram0 # (PAGECOUNT * :INDEX: RamRecSize) ;16 slots, one slot per page of SRAM FirstCmd # 4 CmdMap # 4 Cmd0 # (CMDCOUNT * :INDEX: CmdRecSize) ClearWSEnd # 0 DevCB0 # :INDEX: deviceRecSize DevCB1 # :INDEX: deviceRecSize DevCB2 # :INDEX: deviceRecSize DevCB3 # :INDEX: deviceRecSize DevCB4 # :INDEX: deviceRecSize DevCB5 # :INDEX: deviceRecSize DevCB6 # :INDEX: deviceRecSize DevCB7 # :INDEX: deviceRecSize Cardworkspacesize # 0 ; ; ;============================================================================== ;============================================================================== ; ; Workspace for upto 4 SCSI cards ; ^ 0,WsPtr ListEntry0 # 4 ListEntry1 # 4 ListEntry2 # 4 ListEntry3 # 4 ListHighestTerm # 4 maxCardID # 4 ;0/1/2/3 for 1/2/3/4 SCSI cards SCSIstubsize # 0 LogicalCard0 # :INDEX: Cardworkspacesize LogicalCard1 # :INDEX: Cardworkspacesize LogicalCard2 # :INDEX: Cardworkspacesize LogicalCard3 # :INDEX: Cardworkspacesize SCSIworkspacesize # 0 ; ; ;============================================================================== ;============================================================================== ; ; Control bits in R0 for SWI SCSI_Op ; CTL_TXNONE EQU &00 :SHL: 24 CTL_TXREAD EQU &01 :SHL: 24 CTL_TXWRITE EQU &02 :SHL: 24 CTL_TXRESERVED EQU &03 :SHL: 24 CTL_SCATTER EQU &01 :SHL: 26 CTL_NOESCAPE EQU &01 :SHL: 27 CTL_RETRYONTIMEOUT EQU &01 :SHL: 28 CTL_BACKGROUND EQU &01 :SHL: 29 ; ;>>>Would extra bits for inhibit disconnect and 'this is a message' be useful ;>>>(possibly for internal use only)? ; CTL_INHIBITREQUESTSENSE EQU &01 :SHL: 23 CTL_REPORTUNITATTENTION EQU &01 :SHL: 22 CTL_INHIBITDISCONNECTION EQU &01 :SHL: 21 CTL_INHIBITIDENTIFY EQU &01 :SHL: 20 ; CTL_DOINGREQUESTSENSE EQU &01 :SHL: 19 ; CTL_REJECTQUEUEFULL EQU &01 :SHL: 18 CTL_REJECTDEVICEBUSY EQU &01 :SHL: 17 CTL_REJECTPODULEBUSY EQU &01 :SHL: 16 ; CTL_DOINGRESET EQU &01 :SHL: 15 CTL_DOINGABORTDEVICE EQU &01 :SHL: 14 CTL_DOINGABORTOP EQU &01 :SHL: 13 CTL_DOINGESCAPEDEVICE EQU &01 :SHL: 12 CTL_DOINGTIMEOUT2 EQU &01 :SHL: 11 CTL_DOINGMESSAGEREJECT EQU &01 :SHL: 10 ; ; ; Composite flags for communication at the simplest level, ; ie no disconnection or identify message. ; CTL_DumbDeviceTXNONE EQU CTL_INHIBITDISCONNECTION :OR: CTL_INHIBITIDENTIFY CTL_DumbDeviceTXREAD EQU CTL_DumbDeviceTXNONE :OR: CTL_TXREAD CTL_DumbDeviceTXWRITE EQU CTL_DumbDeviceTXNONE :OR: CTL_TXWRITE ; ; Composite flags for sending messages ; CTL_MessageOnly EQU CTL_INHIBITREQUESTSENSE :OR: CTL_BACKGROUND ; ; ; Actions to be suppressed once MESSAGE_COMMANDCOMPLETE is received ; CTL_Suppress EQU CTL_DOINGABORTOP :OR: CTL_DOINGESCAPEDEVICE :OR: CTL_DOINGTIMEOUT2 ; ; ;============================================================================== ;============================================================================== ; ; Internally the device driver always runs SCSI transfers as background tasks ; that perform a callback on completion/error. The 'foreground' transfers are ; acheived by setting up an internal background handler and looping in the ; foreground until the callback handler indicates completion by writing to ; a block allocated on the stack. The format of this block is:- ; ^ 0 CallBkR0 # 4 ;0 or ->error block CallBkR1 # 4 ;0 or error number CallBkR2 # 4 ; logical address on device where error occured CallRtR3 # 4 ; CallRtR4 # 4 ; CallBkStat # 4 ;RUNNING/IDLE/ERROR CallBkRecSize # 0 ; ; ;============================================================================== END