1. 21 Nov, 2019 2 commits
    • Jeffrey Lee's avatar
      Export more command register bit definitions · 9b92bcef
      Jeffrey Lee authored
      Version 0.17. Tagged as 'PCI-0_17'
      9b92bcef
    • Jeffrey Lee's avatar
      Make PCI_RAMAlloc more robust · 360c9fc5
      Jeffrey Lee authored
      Detail:
      * Use the new OS_Memory 23 memory reservation system to stop other DAs
      claiming exclusive use of the physical memory we want to use for the PCI
      heap
      * Switch to using the new OS_Heap 8 instead of OS_Heap 7, so that memory
      alignment can be handled in terms of physical address insead of logical
      address (avoiding the need to ensure the DA is both logically and
      physically aligned)
      * Make sure the DA max size matches the amount of memory we found, so
      that if we can't get the full 32MB as desired, we don't run the risk of
      growing the DA into a non physically contiguous chunk of RAM
      
      Admin:
      Tested on BB-xM
      360c9fc5
  2. 30 Sep, 2019 1 commit
    • Robert Sprowson's avatar
      Add VID/PID for Pi4 motherboard device · 900f50cb
      Robert Sprowson authored
      Added VIA chip to table of known vendor/devices on motherboards RISC OS runs on.
      Trimmed Makefile clean rule duplication (AAsmModule removes rm).
      
      Version 0.16. Tagged as 'PCI-0_16'
      900f50cb
  3. 10 Sep, 2017 1 commit
    • Jeffrey Lee's avatar
      Fix PCI_RAMAlloc to be physically aligned · eca21ced
      Jeffrey Lee authored
      Detail:
        Although PCI_RAMAlloc claims to allocate blocks at the given alignment, both of the two implementations available (OS_Heap 7 and non-OS_Heap 7) perform the alignment and boundary checks using the logical address of the block. Most of the time this seems to work (few clients need anything greater than 4K page alignment), but for those clients that do need greater alignment, this can easily lead to failure.
        s/Memory - Change PCI_RAMAlloc implementation so that it ensures the block of memory it uses is aligned in both logical and physical spaces. Really it's only the physical alignment we care about, but for now the easiest/safest fix is to match the alignment and stick with the current logically-aligned allocation routines.
        s/GetAll, s/Interface, s/Memory - Use definitions from Hdr:OSMem where appropriate
      Admin:
        Tested on Raspberry Pi 3
        SMP module is now able to correctly get a 16K-aligned block for use as L1PT
        Note that skipping the first few pages of the area recommended by OS_Memory 12 does introduce the risk of non-aligned/non-contiguous areas being returned once the DA becomes close to full. But, for the case where the desired 32MB physically aligned block isn't available and we fall back to smaller block sizes, there's always been the danger that we'll start returning invalid blocks to the client (whether due to the client asking for an alignment we can't satisfy, or the DA exceeding the limits of the aligned area OS_Memory suggested to us)
      
      
      Version 0.15. Tagged as 'PCI-0_15'
      eca21ced
  4. 14 Jul, 2016 1 commit
    • Robert Sprowson's avatar
      Typo · 2b753916
      Robert Sprowson authored
      Podule -> PCI
      Retagged as PCI-0_14.
      2b753916
  5. 16 Aug, 2015 1 commit
    • Jeffrey Lee's avatar
      Documentation update · 11a66772
      Jeffrey Lee authored
      Detail:
        doc/PCI_API - Mention OS_MMUControl 2 in addition to OS_MMUControl 1 when talking about memory barriers
      Admin:
        Documentation change, not tagged
      
      
      Version 0.14. Not tagged
      11a66772
  6. 05 Aug, 2015 1 commit
    • Jeffrey Lee's avatar
      Implement missing memory attribute support for PCI_HardwareAddress & PCI_LogicalAddress · 3c4d00bc
      Jeffrey Lee authored
      Detail:
        s/Interface - Now that OS_Memory 13 allows the cache policy to be specified, PCI_HardwareAddress & PCI_LogicalAddress (which have always been documented as allowing the policy to be specified) can have support for it implemented. PCI_LogicalAddres now also has support for specifying the cacheability implemented (was also documented but unimplemented).
      Admin:
        Tested on Iyonix
      
      
      Version 0.14. Tagged as 'PCI-0_14'
      3c4d00bc
  7. 27 Jan, 2015 1 commit
    • Robert Sprowson's avatar
      Make PCI_MemoryWrite more useful · d67152f4
      Robert Sprowson authored
      Previously the behaviour was thus
      
      MemoryRead
        for (i = 0; i < wordcount; i++)
          buffer[i] = *pcimem
      MemoryWrite
        for (i = 0; i < wordcount; i++)
          pcimem[i] = *buffer
      
      so in the write case the buffer was largely redundant and the SWI would data abort when copying > 1MB as it fell outside the temporary IO assignment from OS_Memory 14. Now it does
      
      MemoryWrite
        for (i = 0; i < wordcount; i++)
          *pcimem = buffer[i]
      
      the most common case where wordcount = 1 is unchanged, and MemoryRead is unchanged.
      Also
       - sprinkle in some more comments
       - make use of mem_to_phys_offset that the HAL is kind enough to have given us, even if it is 0
       - update the capability id bits from PCI-SIG ECN from April 2010
      
      Tested with a parallel port PCI card, which reported it had vendor specific capabilities (InfCap09).
      
      Version 0.13. Tagged as 'PCI-0_13'
      d67152f4
  8. 27 Nov, 2014 2 commits
    • Robert Sprowson's avatar
      Fix for nonsense error and implement a 'todo' action · 19842c18
      Robert Sprowson authored
      An (unlikely) error during ScanBus would end up with an error block pointing to &00000004 as although the V bit was carefully preserved, R0 wasn't.
      Add a RAM flag to remember if the module is operating in no-PCI-bus mode (for PCI_RAMAlloc and PCI_RAMFree) so that the bus access SWIs can return a meaningful error.
      
      Resources/UK/Messages, Errors.s:
       New error message "NoPCIBus".
      GetAll.s:
       Remove unnecessary header includes, and use {FALSE} and {TRUE}.
      Module.s:
       Record result of OS_ReadSysInfo call to determine if there's a PCI bus or not.
       Do fail to initialise in the RAM loading case if ResourceFS register fails.
      Scan.s:
       Preserve R0 if ScanBus returns an error.
       Add some comments.
      Interface.s:
       Inspect flag and report error for those SWIs that are harmful when no bus exists, anything going via ValidateHandle doesn't need to since pci_handles will be 0 in that case.
       Relocate FindFreeHandle to Scan.s.
      
      Tested briefly with and without the "got PCI" bit set, showing the appropriate error being returned.
      
      Version 0.12. Tagged as 'PCI-0_12'
      19842c18
    • Robert Sprowson's avatar
      Add new class codes · 20f0a4c3
      Robert Sprowson authored
      This brings the messages file up to date with "PCI Code and ID Assignment Spec 1.5" from 06-Mar-2014.
      20f0a4c3
  9. 27 Mar, 2012 1 commit
    • Jeffrey Lee's avatar
      Fix asasm 2.00 errors · 1bba5de1
      Jeffrey Lee authored
      Detail:
        s/Scan - asasm's expression parser is a bit stricter than objasm when it comes to dealing with addresses and offsets.
        Add explicit brackets to ensure subtraction is performed first, generating an offset which can be added to ram_abort_handler
      Admin:
        Identical binary under objasm
      
      
      Version 0.11. Retagged as 'PCI-0_11'
      1bba5de1
  10. 02 Feb, 2012 1 commit
    • Jeffrey Lee's avatar
      Fix PCI dynamic area growth logic · ab92495a
      Jeffrey Lee authored
      Detail:
        s/Memory - Fixed a couple of bugs in the dynamic area growth logic that could cause it to fail in some situations:
        * If a boundary value was specified, an invalid boundary value was being passed to OS_Heap when the operation was retried, causing the op to fail
        * The heap grow code was enforcing a minimum alignment of 8 bytes as a way of trying to ensure there'd be enough space for a used block header. However this won't work if the alignment is greater than 4 to begin with; it's much better to just add the extra 4 bytes onto r0 to begin with.
      Admin:
        Tested in Iyonix ROM softload
        Fixes issue reported on forums with floppy access not working:
        http://www.riscosopen.org/forum/forums/5/topics/905
      
      
      Version 0.11. Tagged as 'PCI-0_11'
      ab92495a
  11. 10 Dec, 2011 1 commit
    • Jeffrey Lee's avatar
      Use OS_Heap 7 for allocating IO memory · 5ca343a3
      Jeffrey Lee authored
      Detail:
        s/Commands, s/GetAll, s/Memory, s/Module - Now uses OS_Heap 7 for allocating aligned memory blocks instead of allocating overly large areas to perform manual alignment. Falls back to old method if OS_Heap 7 unavailable.
        Makefile - Removed garbage from end of "dynamic dependencies" line.
      Admin:
        Tested in OMAP3 ROM & Tungsten ROM softload
        PCI shared memory DA now about 300k smaller on a typical Iyonix.
      
      
      Version 0.10. Tagged as 'PCI-0_10'
      5ca343a3
  12. 16 Jun, 2009 1 commit
    • Ben Avison's avatar
      No longer uses unaligned loads on ARMv6 or later · 54f6f429
      Ben Avison authored
      Detail:
        s.Interface line 794: changed to use LDRH - I really can't imagine anyone
          inventing an ARMv3 device with a PCI bus.
        s.Interface line 834: don't rely on rotating loads if ARMv6 is a build
          target - use aligned LDR and explicit rotate instead.
        Added ENTRY directive to permit building of GPA debug listing.
        CPU version is no longer specified in the makefile - it's better to inherit
        it from the build environment now that we actually set it appropriately.
      Admin:
        Builds but not tested.
      
      Version 0.09. Tagged as 'PCI-0_09'
      54f6f429
  13. 11 Jun, 2009 1 commit
    • Ben Avison's avatar
      GET file pathnames changed · 8dd4f685
      Ben Avison authored
      Detail:
        Uses suffixed file extensions for compatiblity with both objasm and asasm.
      Admin:
        Supplied by Peter Naulls, tested at ROOL
      
      Version 0.08. Not tagged
      8dd4f685
  14. 09 May, 2009 1 commit
    • Jeffrey Lee's avatar
      Fix PCI module to not crash on machines without a PCI bus · 19231ae3
      Jeffrey Lee authored
      Detail:
        s/Interface - Avoid unpredictable behaviour if a handle of -1 is given to EnumerateFunctions, FindByClass, etc.
        s/Module - During initialisation use OS_ReadSysInfo 8 to detect PCI bus, since a NullEntry for HAL_PCIAddresses won't return an error.
      Admin:
        Tested on rev C2 beagleboard. Untested on Iyonix, but should be fine.
      
      
      Version 0.08. Tagged as 'PCI-0_08'
      19231ae3
  15. 04 Dec, 2005 1 commit
  16. 21 Jun, 2004 1 commit
    • Mike Hobbs's avatar
      Added support for new STB · 3241948c
      Mike Hobbs authored
      Detail:
        Files modified: s.Memory, s.Module
          Try to get 32MB contiguous memory or successively smaller chunks if not available
      Admin:
        Updated from Kev's machine.
      
      Version 0.06. Tagged as 'PCI-0_06'
      3241948c
  17. 15 Apr, 2003 1 commit
  18. 22 Feb, 2003 1 commit
  19. 22 Nov, 2002 1 commit
  20. 14 Nov, 2002 1 commit
    • Robert Sprowson's avatar
      Removed unused HelpTokens · 7b6ba822
      Robert Sprowson authored
      Removed unused oInterface
      Implemented PCI_MemoryRead,PCI_MemoryWrite,PCI_EnumerateFunctions.
      Resync'd docs with implementation,tidied them up,and expanded some of
      the descriptions.
      Swapped a couple of BHS for BHI so that PCI_FindByXXX can find the last
      thing in the list now.
      Added new service calls to lookup name and vendor strings.
      Added vendor string reason to ReadInfo.
      Now *PCIDEVICES and *PCIINFO report the vendor string and description if
      available,else default to the class code.
      
      Version 0.02. Tagged as 'PCI-0_02'
      7b6ba822
  21. 13 Nov, 2002 1 commit