Commit eca21ced authored by Jeffrey Lee's avatar Jeffrey Lee

Fix PCI_RAMAlloc to be physically aligned

Detail:
  Although PCI_RAMAlloc claims to allocate blocks at the given alignment, both of the two implementations available (OS_Heap 7 and non-OS_Heap 7) perform the alignment and boundary checks using the logical address of the block. Most of the time this seems to work (few clients need anything greater than 4K page alignment), but for those clients that do need greater alignment, this can easily lead to failure.
  s/Memory - Change PCI_RAMAlloc implementation so that it ensures the block of memory it uses is aligned in both logical and physical spaces. Really it's only the physical alignment we care about, but for now the easiest/safest fix is to match the alignment and stick with the current logically-aligned allocation routines.
  s/GetAll, s/Interface, s/Memory - Use definitions from Hdr:OSMem where appropriate
Admin:
  Tested on Raspberry Pi 3
  SMP module is now able to correctly get a 16K-aligned block for use as L1PT
  Note that skipping the first few pages of the area recommended by OS_Memory 12 does introduce the risk of non-aligned/non-contiguous areas being returned once the DA becomes close to full. But, for the case where the desired 32MB physically aligned block isn't available and we fall back to smaller block sizes, there's always been the danger that we'll start returning invalid blocks to the client (whether due to the client asking for an alignment we can't satisfy, or the DA exceeding the limits of the aligned area OS_Memory suggested to us)


Version 0.15. Tagged as 'PCI-0_15'
parent 2b753916
......@@ -11,13 +11,13 @@
GBLS Module_HelpVersion
GBLS Module_ComponentName
GBLS Module_ComponentPath
Module_MajorVersion SETS "0.14"
Module_Version SETA 14
Module_MajorVersion SETS "0.15"
Module_Version SETA 15
Module_MinorVersion SETS ""
Module_Date SETS "16 Aug 2015"
Module_ApplicationDate SETS "16-Aug-15"
Module_Date SETS "10 Sep 2017"
Module_ApplicationDate SETS "10-Sep-17"
Module_ComponentName SETS "PCI"
Module_ComponentPath SETS "castle/RiscOS/Sources/HWSupport/PCI"
Module_FullVersion SETS "0.14"
Module_HelpVersion SETS "0.14 (16 Aug 2015)"
Module_FullVersion SETS "0.15"
Module_HelpVersion SETS "0.15 (10 Sep 2017)"
END
/* (0.14)
/* (0.15)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.14
#define Module_MajorVersion_CMHG 0.15
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 16 Aug 2015
#define Module_Date_CMHG 10 Sep 2017
#define Module_MajorVersion "0.14"
#define Module_Version 14
#define Module_MajorVersion "0.15"
#define Module_Version 15
#define Module_MinorVersion ""
#define Module_Date "16 Aug 2015"
#define Module_Date "10 Sep 2017"
#define Module_ApplicationDate "16-Aug-15"
#define Module_ApplicationDate "10-Sep-17"
#define Module_ComponentName "PCI"
#define Module_ComponentPath "castle/RiscOS/Sources/HWSupport/PCI"
#define Module_FullVersion "0.14"
#define Module_HelpVersion "0.14 (16 Aug 2015)"
#define Module_LibraryVersionInfo "0:14"
#define Module_FullVersion "0.15"
#define Module_HelpVersion "0.15 (10 Sep 2017)"
#define Module_LibraryVersionInfo "0:15"
......@@ -34,6 +34,7 @@
GET Hdr:ResourceFS
GET Hdr:MsgTrans
GET Hdr:Heap
GET Hdr:OSMem
GET VersionASM
......
......@@ -253,7 +253,7 @@ IORead ROUT
BNE BadAccessSize
Push "r0,r2,r3,lr"
ADD r1, r0, r11
MOV r0, #14
MOV r0, #OSMemReason_AccessPhysAddr
SWI XOS_Memory ; r2 -> logical addr, r3 = old state
LDR r11, [sp, #4]
BVS %FT99
......@@ -261,7 +261,7 @@ IORead ROUT
LDRLOB r1, [r2]
LDREQH r1, [r2]
LDRHI r1, [r2]
MOV r0, #15
MOV r0, #OSMemReason_ReleasePhysAddr
MOV r2, r1
MOV r1, r3
SWI XOS_Memory
......@@ -283,7 +283,7 @@ IOWrite ROUT
BNE BadAccessSize
Push "r0-r3,lr"
ADD r1, r0, r11
MOV r0, #14
MOV r0, #OSMemReason_AccessPhysAddr
SWI XOS_Memory ; r2 -> logical addr, r3 = old state
LDMIB sp, {r1, r11}
BVS %FT99
......@@ -291,7 +291,7 @@ IOWrite ROUT
STRLOB r1, [r2]
STREQH r1, [r2]
STRHI r1, [r2]
MOV r0, #15
MOV r0, #OSMemReason_ReleasePhysAddr
MOV r1, r3
SWI XOS_Memory
BVS %FT99
......@@ -308,7 +308,7 @@ MemoryRead ROUT
Push "r0-r3,lr"
BIC r1, r0, #3 ; force it to be word aligned
ADD r1, r11, r1
MOV r0, #14
MOV r0, #OSMemReason_AccessPhysAddr
SWI XOS_Memory ; r2 -> logical addr, r3 = old state
LDR r11, [sp, #8] ; points to destination buffer
LDR r12, [sp, #4] ; the length to do
......@@ -320,7 +320,7 @@ MemoryRead ROUT
TEQ r11, r12
BNE %BT80
MOV r0, #15
MOV r0, #OSMemReason_ReleasePhysAddr
MOV r1, r3
SWI XOS_Memory ; release
BVS %FT99
......@@ -334,7 +334,7 @@ MemoryWrite
Push "r0-r3,lr"
BIC r1, r0, #3 ; force it to be word aligned
ADD r1, r11, r1
MOV r0, #14
MOV r0, #OSMemReason_AccessPhysAddr
SWI XOS_Memory ; r2 -> logical addr, r3 = old state
LDR r11, [sp, #8] ; points to source buffer
LDR r12, [sp, #4] ; the length to do
......@@ -346,7 +346,7 @@ MemoryWrite
TEQ r11, r12
BNE %BT90
MOV r0, #15
MOV r0, #OSMemReason_ReleasePhysAddr
MOV r1, r3
SWI XOS_Memory ; release
BVS %FT99
......@@ -462,7 +462,7 @@ HardwareAddress
LDRNE lr, pci_io_to_phys_offset
LDREQ lr, pci_mem_to_phys_offset
ADD r1, r1, lr
MOV r0, #13
MOV r0, #OSMemReason_MapIOPermanent
AND lr, r10, #&1F0 ; B+C+policy bits
ORR r0, r0, lr, LSL #4
TST r10, #1:SHL:9 ; Access privileges given
......@@ -497,7 +497,7 @@ LogicalAddress
ADD r1, r1, lr
AND r0, r0, #&1F0 ; B+C+policy bits
MOV r0, r0, LSL #4
ORR r0, r0, #13
ORR r0, r0, #OSMemReason_MapIOPermanent
SWI XOS_Memory
STRVS r0, [sp]
MOVVC r4, r3
......
......@@ -174,11 +174,10 @@ InitDA
MOVVC r0, #0
STRVCB r0, [r2, r3]
MOVVC r8, r2
SWIVC XOS_ReadMemMapInfo
MOVVC r2, r0 ; initial size = 1 page
MOVVC r0, #0
MOVVC r0, #DAReason_Create
MOVVC r1, #-1
STRVC r1, mempool_base_ppn
MOVVC r2, #0
MOVVC r3, #-1
MOVVC r4, #2_00100010 ; SVC only, B, ~C, draggable
ORRVC r4, r4, #&100 ; requires specific physical pages
......@@ -197,10 +196,16 @@ InitDA
20 STR r1, mempool_da_number
STR r3, mempool_base_log
STR r3, mempool_free
MOV r0, #HeapReason_Init
MOV r1, r3
MOV r3, r2
SWI XOS_Heap
; Grow by one page so we can init the heap
; (can't do the initial grow during DA create since the pre-grow handler needs to know the logical base)
SWI XOS_ReadMemMapInfo
MOVVC r1, r0
LDRVC r0, mempool_da_number
SWIVC XOS_ChangeDynamicArea
MOVVC r0, #HeapReason_Init
MOVVC r3, r1
LDRVC r1, mempool_base_log
SWIVC XOS_Heap
Pull "r0-r8,pc",VC
; error case
STR r0,[sp]
......@@ -210,7 +215,7 @@ InitDA
KillDA
Push "r0-r1,lr"
MOV r0, #1
MOV r0, #DAReason_Remove
LDR r1, mempool_da_number
CMP r1, #0
[ DebugMemory
......@@ -260,7 +265,7 @@ PreGrow Entry "r0-r3"
MOV r1, #32*1024*1024 ; Try for 32M, 4M aligned
MOV r2, #22
02 MOV r0, #12
02 MOV r0, #OSMemReason_RecommendPage
SWI XOS_Memory
BVC %FT03
MOV r1, r1, LSR #1 ; If we can't get it, halve both
......@@ -271,9 +276,20 @@ PreGrow Entry "r0-r3"
03
[ DebugMemory
DREG r3, "PPN suggested ",,Integer
]
; Skip the first few pages of the region, to ensure physical alignment and logical alignment match
; (all our allocation functions work by aligning based around logical addresses, when really what the client wants is physically aligned memory)
MOV r0, #1
MOV r2, r0, LSL r2
SUB r2, r2, #1
LDR r0, mempool_base_log
AND r0, r0, r2
ADD r3, r3, r0, LSR #12
[ DebugMemory
DREG r3, "PPN aligned ",,Integer
]
STR r3, mempool_base_ppn
MOV r0, #2_100001:SHL:8
MOV r0, #(2_100001:SHL:8) + OSMemReason_Convert
ADR r1, mempool_base_ppn
MOV r2, #1
SWI XOS_Memory
......
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