Commits (7)
  • Robert Sprowson's avatar
    Add VID/PID for Pi4 motherboard device · 900f50cb
    Robert Sprowson authored
    Added VIA chip to table of known vendor/devices on motherboards RISC OS runs on.
    Trimmed Makefile clean rule duplication (AAsmModule removes rm).
    
    Version 0.16. Tagged as 'PCI-0_16'
    900f50cb
  • Jeffrey Lee's avatar
    Make PCI_RAMAlloc more robust · 360c9fc5
    Jeffrey Lee authored
    Detail:
    * Use the new OS_Memory 23 memory reservation system to stop other DAs
    claiming exclusive use of the physical memory we want to use for the PCI
    heap
    * Switch to using the new OS_Heap 8 instead of OS_Heap 7, so that memory
    alignment can be handled in terms of physical address insead of logical
    address (avoiding the need to ensure the DA is both logically and
    physically aligned)
    * Make sure the DA max size matches the amount of memory we found, so
    that if we can't get the full 32MB as desired, we don't run the risk of
    growing the DA into a non physically contiguous chunk of RAM
    
    Admin:
    Tested on BB-xM
    360c9fc5
  • Jeffrey Lee's avatar
    Export more command register bit definitions · 9b92bcef
    Jeffrey Lee authored
    Version 0.17. Tagged as 'PCI-0_17'
    9b92bcef
  • Robert Sprowson's avatar
    Allow mappings from PCI address space to 64b I/O memory · 462f20a7
    Robert Sprowson authored
    Extend the previously 32b offsets from PCI to ARM (physical) addresses as retrieved with HAL_PCIAddresses to instead by 64b offsets. After having applied the offset, choose the 64b versions of OS_Memory to map them in.
    No SWI interfaces are harmed in the making of this change.
    462f20a7
  • Robert Sprowson's avatar
    Adopt NEC OHCI card lookup · c490d235
    Robert Sprowson authored
    With a view to removing the vendor specific text from the generic OHCI driver at some point in future.
    c490d235
  • Robert Sprowson's avatar
    Accept old & new table format · 117f576d
    Robert Sprowson authored
    Just in case anyone tries loading this on an old HAL, remap 28 byte address table format to 40 byte.
    
    Version 0.18. Tagged as 'PCI-0_18'
    117f576d
  • Robert Sprowson's avatar
    Messages update · cf9190c9
    Robert Sprowson authored
    Add status bit 3, an extra flag bit for PCIe non-MSI interrupts.
    Add the recent class codes from the PCI-SIG rev 1.11 assignments (Jan 2019 edition).
    
    Version 0.19. Tagged as 'PCI-0_19'
    cf9190c9
...@@ -14,12 +14,6 @@ ...@@ -14,12 +14,6 @@
# #
# Makefile for PCI # Makefile for PCI
# #
# ***********************************
# *** C h a n g e L i s t ***
# ***********************************
# Date Name Description
# ---- ---- -----------
# 06-Jun-00 SNB Recreated using makefile fragments
COMPONENT = PCI COMPONENT = PCI
...@@ -39,11 +33,4 @@ ASFLAGS = ${OPTIONS} ...@@ -39,11 +33,4 @@ ASFLAGS = ${OPTIONS}
include StdTools include StdTools
include AAsmModule include AAsmModule
#
# Generic rules:
#
clean::
${WIPE} rm ${WFLAGS}
@@echo ${COMPONENT}: cleaned
# Dynamic dependencies: # Dynamic dependencies:
...@@ -50,6 +50,7 @@ InfCmd7:Address/data stepping enabled ...@@ -50,6 +50,7 @@ InfCmd7:Address/data stepping enabled
InfCmd8:SERR# driver enabled InfCmd8:SERR# driver enabled
InfCmd9/InfBrC7:Fast back-to-back enabled InfCmd9/InfBrC7:Fast back-to-back enabled
InfSt?3:Emulated interrupt pending
InfSt?4:Capabilities list implemented InfSt?4:Capabilities list implemented
InfSt?5:66MHz capable InfSt?5:66MHz capable
InfSt?7:Fast back-to-back capable InfSt?7:Fast back-to-back capable
...@@ -107,6 +108,7 @@ C0105??:ATA controller ...@@ -107,6 +108,7 @@ C0105??:ATA controller
C0106??:SATA controller C0106??:SATA controller
C0107??:Serially attached SCSI controller C0107??:Serially attached SCSI controller
C0108??:Non volatile memory controller C0108??:Non volatile memory controller
C0109??:Universal flash storage controller
C01????:Mass storage controller C01????:Mass storage controller
C020000:Ethernet controller C020000:Ethernet controller
C020100:Token Ring controller C020100:Token Ring controller
...@@ -142,6 +144,7 @@ C060700:CardBus bridge ...@@ -142,6 +144,7 @@ C060700:CardBus bridge
C0608??:RACEway bridge C0608??:RACEway bridge
C0609??:Semi transparent PCI-to-PCI bridge C0609??:Semi transparent PCI-to-PCI bridge
C060A00:Infiniband to PCI bridge C060A00:Infiniband to PCI bridge
C060B00:Advanced Switching to PCI bridge
C06????:Bridge device C06????:Bridge device
C070000:Generic XT-compatible serial controller C070000:Generic XT-compatible serial controller
C070001:16450-compatible serial controller C070001:16450-compatible serial controller
...@@ -181,6 +184,7 @@ C080301:ISA RTC controller ...@@ -181,6 +184,7 @@ C080301:ISA RTC controller
C080400:Generic PCI Hot-Plug controller C080400:Generic PCI Hot-Plug controller
C080500:SD controller C080500:SD controller
C080600:IOMMU C080600:IOMMU
C080700:Root Complex Event Collector
C08????:System peripheral C08????:System peripheral
C090000:Keyboard controller C090000:Keyboard controller
C090100:Digitiser (pen) C090100:Digitiser (pen)
...@@ -215,14 +219,15 @@ C0C0600:Infiniband controller ...@@ -215,14 +219,15 @@ C0C0600:Infiniband controller
C0C0700:IPMI SMIC interface C0C0700:IPMI SMIC interface
C0C0800:SERCOS interface C0C0800:SERCOS interface
C0C0900:CAN bus C0C0900:CAN bus
C0C0A00:MIPI I3C controller
C0C????:Serial bus controller C0C????:Serial bus controller
C0D0000:iRDA controller C0D0000:iRDA controller
C0D0100:Consumer IR controller C0D0100:Consumer IR controller
C0D1000:RF controller C0D1000:RF controller
C0D1100:Bluetooth controller C0D1100:Bluetooth controller
C0D1200:Broadband controller C0D1200:Broadband controller
C0D2000:802.1a controller C0D2000:802.11a controller
C0D2100:802.1b controller C0D2100:802.11b controller
C0D????:Wireless controller C0D????:Wireless controller
C0E????:I2O controller C0E????:I2O controller
C0F0100:Satellite TV controller C0F0100:Satellite TV controller
...@@ -243,17 +248,21 @@ C13????:Non essential instrumentation ...@@ -243,17 +248,21 @@ C13????:Non essential instrumentation
C??????:Unknown PCI device (class %0) C??????:Unknown PCI device (class %0)
# Preferred vendor names # Preferred vendor names
V1033:NEC
V10B9:Acer V10B9:Acer
V1106:VIA
V3388:HiNT V3388:HiNT
V8086:Intel V8086:Intel
# Preferred device names # Preferred device names
D10330035:Open HCI USB Controller
D10B91533:M1535+ south bridge D10B91533:M1535+ south bridge
D10B95229:M5229 ATA controller D10B95229:M5229 ATA controller
D10B95237:M5237 OpenHCI USB controller D10B95237:M5237 OpenHCI USB controller
D10B95451:M5451 AC'97 controller D10B95451:M5451 AC'97 controller
D10B95457:M5457 software modem interface D10B95457:M5457 software modem interface
D10B97101:M7101 power management controller D10B97101:M7101 power management controller
D11063483:VL805 XHCI USB controller
D33880026:HB2 PCI-to-PCI bridge D33880026:HB2 PCI-to-PCI bridge
D8086B154:21154 PCI-to-PCI bridge D8086B154:21154 PCI-to-PCI bridge
D8086100E:82540 Gigabit Ethernet controller D8086100E:82540 Gigabit Ethernet controller
; ;
; This file is automatically maintained by srccommit, do not edit manually. ; This file is automatically maintained by srccommit, do not edit manually.
; Last processed by srccommit version: 1.1.
; ;
GBLS Module_MajorVersion GBLS Module_MajorVersion
GBLA Module_Version GBLA Module_Version
...@@ -10,14 +9,12 @@ ...@@ -10,14 +9,12 @@
GBLS Module_ApplicationDate GBLS Module_ApplicationDate
GBLS Module_HelpVersion GBLS Module_HelpVersion
GBLS Module_ComponentName GBLS Module_ComponentName
GBLS Module_ComponentPath Module_MajorVersion SETS "0.19"
Module_MajorVersion SETS "0.15" Module_Version SETA 19
Module_Version SETA 15
Module_MinorVersion SETS "" Module_MinorVersion SETS ""
Module_Date SETS "10 Sep 2017" Module_Date SETS "29 Aug 2020"
Module_ApplicationDate SETS "10-Sep-17" Module_ApplicationDate SETS "29-Aug-20"
Module_ComponentName SETS "PCI" Module_ComponentName SETS "PCI"
Module_ComponentPath SETS "castle/RiscOS/Sources/HWSupport/PCI" Module_FullVersion SETS "0.19"
Module_FullVersion SETS "0.15" Module_HelpVersion SETS "0.19 (29 Aug 2020)"
Module_HelpVersion SETS "0.15 (10 Sep 2017)"
END END
/* (0.15) /* (0.19)
* *
* This file is automatically maintained by srccommit, do not edit manually. * This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
* *
*/ */
#define Module_MajorVersion_CMHG 0.15 #define Module_MajorVersion_CMHG 0.19
#define Module_MinorVersion_CMHG #define Module_MinorVersion_CMHG
#define Module_Date_CMHG 10 Sep 2017 #define Module_Date_CMHG 29 Aug 2020
#define Module_MajorVersion "0.15" #define Module_MajorVersion "0.19"
#define Module_Version 15 #define Module_Version 19
#define Module_MinorVersion "" #define Module_MinorVersion ""
#define Module_Date "10 Sep 2017" #define Module_Date "29 Aug 2020"
#define Module_ApplicationDate "10-Sep-17" #define Module_ApplicationDate "29-Aug-20"
#define Module_ComponentName "PCI" #define Module_ComponentName "PCI"
#define Module_ComponentPath "castle/RiscOS/Sources/HWSupport/PCI"
#define Module_FullVersion "0.15" #define Module_FullVersion "0.19"
#define Module_HelpVersion "0.15 (10 Sep 2017)" #define Module_HelpVersion "0.19 (29 Aug 2020)"
#define Module_LibraryVersionInfo "0:15" #define Module_LibraryVersionInfo "0:19"
...@@ -138,6 +138,15 @@ PCIConf1_BridgeControl # 2 ...@@ -138,6 +138,15 @@ PCIConf1_BridgeControl # 2
PCICmd_IO * 1:SHL:0 PCICmd_IO * 1:SHL:0
PCICmd_Memory * 1:SHL:1 PCICmd_Memory * 1:SHL:1
PCICmd_BusMaster * 1:SHL:2
PCICmd_SpecialCycles * 1:SHL:3
PCICmd_MemWriteInvalidate * 1:SHL:4
PCICmd_VGAPaletteSnoop * 1:SHL:5
PCICmd_ReportParityErrors * 1:SHL:6
PCICmd_Stepping * 1:SHL:7
PCICmd_ReportSystemErrors * 1:SHL:8
PCICmd_FastBackToBack * 1:SHL:9
PCICmd_MaskInterrupt * 1:SHL:10
PCISta_Capabilities * 1:SHL:4 PCISta_Capabilities * 1:SHL:4
......
...@@ -31,5 +31,6 @@ ...@@ -31,5 +31,6 @@
MakeInternatErrorBlock NDallas MakeInternatErrorBlock NDallas
MakeInternatErrorBlock CDATBufferOverflow,,"BufOFlo" MakeInternatErrorBlock CDATBufferOverflow,,"BufOFlo"
MakeErrorBlock ModuleBadSWI MakeErrorBlock ModuleBadSWI
MakeErrorBlock ChDynamNotAllMoved
END END
...@@ -246,14 +246,17 @@ IORead ROUT ...@@ -246,14 +246,17 @@ IORead ROUT
LDRB r10, pcibus_supported LDRB r10, pcibus_supported
TEQ r10, #0 TEQ r10, #0
BEQ BadWithNoBus BEQ BadWithNoBus
LDR r11, pci_io_to_phys_offset LDR r10, pci_io_to_phys_offset + 0
LDR r11, pci_io_to_phys_offset + 4
TEQ r2, #1 TEQ r2, #1
TEQNE r2, #2 TEQNE r2, #2
TEQNE r2, #4 TEQNE r2, #4
BNE BadAccessSize BNE BadAccessSize
Push "r0,r2,r3,lr" Push "r0,r2,r3,lr"
ADD r1, r0, r11 ADDS r1, r10, r0
MOV r0, #OSMemReason_AccessPhysAddr ADCS r2, r11, #0
MOVNE r0, #OSMemReason_AccessPhysAddr64
MOVEQ r0, #OSMemReason_AccessPhysAddr
SWI XOS_Memory ; r2 -> logical addr, r3 = old state SWI XOS_Memory ; r2 -> logical addr, r3 = old state
LDR r11, [sp, #4] LDR r11, [sp, #4]
BVS %FT99 BVS %FT99
...@@ -276,14 +279,17 @@ IOWrite ROUT ...@@ -276,14 +279,17 @@ IOWrite ROUT
LDRB r10, pcibus_supported LDRB r10, pcibus_supported
TEQ r10, #0 TEQ r10, #0
BEQ BadWithNoBus BEQ BadWithNoBus
LDR r11, pci_io_to_phys_offset LDR r10, pci_io_to_phys_offset + 0
LDR r11, pci_io_to_phys_offset + 4
TEQ r2, #1 TEQ r2, #1
TEQNE r2, #2 TEQNE r2, #2
TEQNE r2, #4 TEQNE r2, #4
BNE BadAccessSize BNE BadAccessSize
Push "r0-r3,lr" Push "r0-r3,lr"
ADD r1, r0, r11 ADDS r1, r10, r0
MOV r0, #OSMemReason_AccessPhysAddr ADCS r2, r11, #0
MOVNE r0, #OSMemReason_AccessPhysAddr64
MOVEQ r0, #OSMemReason_AccessPhysAddr
SWI XOS_Memory ; r2 -> logical addr, r3 = old state SWI XOS_Memory ; r2 -> logical addr, r3 = old state
LDMIB sp, {r1, r11} LDMIB sp, {r1, r11}
BVS %FT99 BVS %FT99
...@@ -304,11 +310,14 @@ MemoryRead ROUT ...@@ -304,11 +310,14 @@ MemoryRead ROUT
LDRB r10, pcibus_supported LDRB r10, pcibus_supported
TEQ r10, #0 TEQ r10, #0
BEQ BadWithNoBus BEQ BadWithNoBus
LDR r11, pci_mem_to_phys_offset LDR r10, pci_mem_to_phys_offset + 0
LDR r11, pci_mem_to_phys_offset + 4
Push "r0-r3,lr" Push "r0-r3,lr"
BIC r1, r0, #3 ; force it to be word aligned BIC r1, r0, #3 ; force it to be word aligned
ADD r1, r11, r1 ADDS r1, r10, r1
MOV r0, #OSMemReason_AccessPhysAddr ADCS r2, r11, #0
MOVNE r0, #OSMemReason_AccessPhysAddr64
MOVEQ r0, #OSMemReason_AccessPhysAddr
SWI XOS_Memory ; r2 -> logical addr, r3 = old state SWI XOS_Memory ; r2 -> logical addr, r3 = old state
LDR r11, [sp, #8] ; points to destination buffer LDR r11, [sp, #8] ; points to destination buffer
LDR r12, [sp, #4] ; the length to do LDR r12, [sp, #4] ; the length to do
...@@ -319,22 +328,20 @@ MemoryRead ROUT ...@@ -319,22 +328,20 @@ MemoryRead ROUT
STR r14, [r11], #4 STR r14, [r11], #4
TEQ r11, r12 TEQ r11, r12
BNE %BT80 BNE %BT80
B %FT98
MOV r0, #OSMemReason_ReleasePhysAddr
MOV r1, r3
SWI XOS_Memory ; release
BVS %FT99
Pull "r0-r3,pc"
MemoryWrite MemoryWrite
LDRB r10, pcibus_supported LDRB r10, pcibus_supported
TEQ r10, #0 TEQ r10, #0
BEQ BadWithNoBus BEQ BadWithNoBus
LDR r11, pci_mem_to_phys_offset LDR r10, pci_mem_to_phys_offset + 0
LDR r11, pci_mem_to_phys_offset + 4
Push "r0-r3,lr" Push "r0-r3,lr"
BIC r1, r0, #3 ; force it to be word aligned BIC r1, r0, #3 ; force it to be word aligned
ADD r1, r11, r1 ADDS r1, r10, r1
MOV r0, #OSMemReason_AccessPhysAddr ADCS r2, r11, #0
MOVNE r0, #OSMemReason_AccessPhysAddr64
MOVEQ r0, #OSMemReason_AccessPhysAddr
SWI XOS_Memory ; r2 -> logical addr, r3 = old state SWI XOS_Memory ; r2 -> logical addr, r3 = old state
LDR r11, [sp, #8] ; points to source buffer LDR r11, [sp, #8] ; points to source buffer
LDR r12, [sp, #4] ; the length to do LDR r12, [sp, #4] ; the length to do
...@@ -345,7 +352,7 @@ MemoryWrite ...@@ -345,7 +352,7 @@ MemoryWrite
STR r14, [r2] STR r14, [r2]
TEQ r11, r12 TEQ r11, r12
BNE %BT90 BNE %BT90
98
MOV r0, #OSMemReason_ReleasePhysAddr MOV r0, #OSMemReason_ReleasePhysAddr
MOV r1, r3 MOV r1, r3
SWI XOS_Memory ; release SWI XOS_Memory ; release
...@@ -457,12 +464,17 @@ HardwareAddress ...@@ -457,12 +464,17 @@ HardwareAddress
TST r10, #1:SHL:31 ; Query only TST r10, #1:SHL:31 ; Query only
BNE %FT40 BNE %FT40
LDRB r0, [r11, #PCIAddress_Flags] LDRB r0, [r11, #PCIAddress_Flags]
Push "r1" Push "r1, r2"
MOV r3, r2
TST r0, #Address_IO TST r0, #Address_IO
LDRNE lr, pci_io_to_phys_offset ADRNE r2, pci_io_to_phys_offset
LDREQ lr, pci_mem_to_phys_offset ADREQ r2, pci_mem_to_phys_offset
ADD r1, r1, lr LDMIA r2, {r2, lr}
MOV r0, #OSMemReason_MapIOPermanent ADDS r1, r2, r1
ADCS r2, lr, #0
MOVNE r0, #OSMemReason_MapIO64Permanent
MOVEQ r0, #OSMemReason_MapIOPermanent
MOVEQ r2, r3
AND lr, r10, #&1F0 ; B+C+policy bits AND lr, r10, #&1F0 ; B+C+policy bits
ORR r0, r0, lr, LSL #4 ORR r0, r0, lr, LSL #4
TST r10, #1:SHL:9 ; Access privileges given TST r10, #1:SHL:9 ; Access privileges given
...@@ -470,7 +482,7 @@ HardwareAddress ...@@ -470,7 +482,7 @@ HardwareAddress
ANDNE lr, r10, #2_1111 ANDNE lr, r10, #2_1111
ORRNE r0, r0, lr, LSL #24 ORRNE r0, r0, lr, LSL #24
SWI XOS_Memory SWI XOS_Memory
Pull "r1" Pull "r1, r2"
MOVVC r4, r3 MOVVC r4, r3
40 LDRVCB r0, [r11, #PCIAddress_Flags] 40 LDRVCB r0, [r11, #PCIAddress_Flags]
90 ADD sp, sp, #8 90 ADD sp, sp, #8
...@@ -490,18 +502,23 @@ LogicalAddress ...@@ -490,18 +502,23 @@ LogicalAddress
LDRB r10, pcibus_supported LDRB r10, pcibus_supported
TEQ r10, #0 TEQ r10, #0
BEQ BadWithNoBus BEQ BadWithNoBus
Push "r0,r1,r3,lr" Push "r0-r3,lr"
MOV r3, r2
TST r0, #1:SHL:30 TST r0, #1:SHL:30
LDRNE lr, pci_io_to_phys_offset ADRNE r2, pci_io_to_phys_offset
LDREQ lr, pci_mem_to_phys_offset ADREQ r2, pci_mem_to_phys_offset
ADD r1, r1, lr LDMIA r2, {r2, lr}
ADDS r1, r2, r1
ADCS r2, lr, #0
AND r0, r0, #&1F0 ; B+C+policy bits AND r0, r0, #&1F0 ; B+C+policy bits
MOV r0, r0, LSL #4 MOV r0, r0, LSL #4
ORR r0, r0, #OSMemReason_MapIOPermanent ORRNE r0, r0, #OSMemReason_MapIO64Permanent
ORREQ r0, r0, #OSMemReason_MapIOPermanent
MOVEQ r2, r3
SWI XOS_Memory SWI XOS_Memory
STRVS r0, [sp] STRVS r0, [sp]
MOVVC r4, r3 MOVVC r4, r3
Pull "r0,r1,r3,pc" Pull "r0-r3,pc"
; **************************************************************************** ; ****************************************************************************
; ;
...@@ -537,6 +554,8 @@ LogicalAddress ...@@ -537,6 +554,8 @@ LogicalAddress
; Bit 12 ==> Ethernet address (low 32 bits) ; Bit 12 ==> Ethernet address (low 32 bits)
; Bit 13 ==> Ethernet address (high 16 bits) ; Bit 13 ==> Ethernet address (high 16 bits)
; Bit 14 ==> Logical number of the primary DMA channel ; Bit 14 ==> Logical number of the primary DMA channel
; Bit 15 ==> Number of BARs
; Bit 16 ==> Pointer to vendor (0 for none)
ReadInfo ROUT ReadInfo ROUT
Push "r0-r6, lr" Push "r0-r6, lr"
......
...@@ -13,32 +13,33 @@ ...@@ -13,32 +13,33 @@
; limitations under the License. ; limitations under the License.
; ;
RAMAlloc RAMAlloc
Push "r1-r4,lr" Push "r1-r5,lr"
LDR lr, mempool_base_log LDR lr, mempool_base_log
TEQ lr, #0 TEQ lr, #0
BLEQ InitDA BLEQ InitDA
Pull "r1-r4,pc",VS Pull "r1-r5,pc",VS
[ DebugMemory [ DebugMemory
DREG r0, "Requested size ",cc DREG r0, "Requested size ",cc
DREG r1, ", alignment ",cc DREG r1, ", alignment ",cc
DREG r2, ", boundary limitation " DREG r2, ", boundary limitation "
] ]
LDRB r3, osheap7_supported LDRB r3, osheap8_supported
CMP r3, #0 CMP r3, #0
BEQ NoOSHeap7 BEQ NoOSHeap8
MOV r4, r2 MOV r4, r2
MOV r3, r0 MOV r3, r0
MOV r2, r1 MOV r2, r1
MOV r0, #HeapReason_GetAligned MOV r0, #HeapReason_GetSkewAligned
LDR r1, mempool_base_log LDR r1, mempool_base_log
LDR r5, mempool_base_phys
SWI XOS_Heap SWI XOS_Heap
BVC GotAlloced BVC GotAlloced
LDR r14, [r0] LDR r14, [r0]
TEQ r14, #ErrorNumber_HeapFail_Alloc TEQ r14, #ErrorNumber_HeapFail_Alloc
Pull "r1-r4,pc",NE Pull "r1-r5,pc",NE
; Grow heap ; Grow heap
LDR r0, [r1, #8] ; heap base offset LDR r0, [r1, #8] ; heap base offset
ADD r0, r0, r1 ; heap base ptr ADD r0, r0, r5 ; converted to physical address
; Add some breathing room to ensure a free block plus used block header will fit ; Add some breathing room to ensure a free block plus used block header will fit
ADD r0, r0, #12 ADD r0, r0, #12
; Round up heap base ptr to required alignment ; Round up heap base ptr to required alignment
...@@ -60,19 +61,27 @@ RAMAlloc ...@@ -60,19 +61,27 @@ RAMAlloc
ADD r0, r0, r4 ADD r0, r0, r4
BIC r0, r0, r4 BIC r0, r0, r4
BoundaryOK BoundaryOK
ADD r0, r0, r3 ADD r0, r0, r3 ; required physical end addr of heap
LDR r2, [r1, #12] ; heap end offset SUB r0, r0, r5 ; required heap size
SUB r0, r0, r1 ; New base offset LDR r2, [r1, #12] ; current heap end offset
ADD r4, r4, #1 ADD r4, r4, #1
SUB r1, r0, r2 ; Grow amount SUB r1, r0, r2 ; Grow amount
LDR r0, mempool_da_number LDR r0, mempool_da_number
SWI XOS_ChangeDynamicArea SWI XOS_ChangeDynamicArea
; Try again ; Try again
MOVVC r0, #HeapReason_GetAligned MOVVC r0, #HeapReason_GetSkewAligned
LDRVC r1, mempool_base_log LDRVC r1, mempool_base_log
LDRVC r2, [sp] LDRVC r2, [sp]
SWIVC XOS_Heap SWIVC XOS_Heap
Pull "r1-r4,pc",VS [ DebugMemory
BVC %FT90
LDR r1,[r0],#4
DREG r1,"Error ",cc
DSTRING r0
SUB r0,r0,#4
90
]
Pull "r1-r5,pc",VS
GotAlloced GotAlloced
[ DebugMemory [ DebugMemory
...@@ -88,9 +97,15 @@ GotAlloced ...@@ -88,9 +97,15 @@ GotAlloced
DREG r1, ", physical address = " DREG r1, ", physical address = "
] ]
ADD sp, sp, #4 ADD sp, sp, #4
Pull "r2-r4,pc" Pull "r2-r5,pc"
NoOSHeap7 NoOSHeap8
; Check requested alignment against the alignment of the memory we
; reserved - anything larger than the memory alignment can't be dealt
; with by this fallback implementation
LDR r3, mempool_alignment
MOVS lr, r1, LSR r3
BNE BadAlign
CMP r2, r1 CMP r2, r1
MOVLO r2, r1 ; cheaty cheaty MOVLO r2, r1 ; cheaty cheaty
LDR r1, mempool_base_log LDR r1, mempool_base_log
...@@ -100,10 +115,10 @@ NoOSHeap7 ...@@ -100,10 +115,10 @@ NoOSHeap7
ADDHI r3, r0, r4 ADDHI r3, r0, r4
MOV r0, #HeapReason_Get MOV r0, #HeapReason_Get
SWI XOS_Heap SWI XOS_Heap
BVC GotAllocedNoOSHeap7 BVC GotAllocedNoOSHeap8
LDR r14, [r0] LDR r14, [r0]
TEQ r14, #ErrorNumber_HeapFail_Alloc TEQ r14, #ErrorNumber_HeapFail_Alloc
Pull "r1-r4,pc",NE Pull "r1-r5,pc",NE
; Grow heap ; Grow heap
LDR r0, [r1, #8] ; heap base offset LDR r0, [r1, #8] ; heap base offset
LDR r1, [r1, #12] ; heap end offset LDR r1, [r1, #12] ; heap end offset
...@@ -117,19 +132,21 @@ NoOSHeap7 ...@@ -117,19 +132,21 @@ NoOSHeap7
MOVVC r0, #HeapReason_Get MOVVC r0, #HeapReason_Get
LDRVC r1, mempool_base_log LDRVC r1, mempool_base_log
SWIVC XOS_Heap SWIVC XOS_Heap
Pull "r1-r4,pc",VS Pull "r1-r5,pc",VS
GotAllocedNoOSHeap7 GotAllocedNoOSHeap8
[ DebugMemory [ DebugMemory
DREG r2, "Allocated block at ",cc DREG r2, "Allocated block at ",cc
DREG r3, ", size = " DREG r3, ", size = "
] ]
ADD r0, r2, #4 ADD r0, r2, #4
CMP r4, #4 CMP r4, #4
SUBHI lr, r2, r1 ; align relative to heap start
SUBHI r3, r4, #1 SUBHI r3, r4, #1
ADDHI r0, r2, r3 ADDHI r0, lr, r3
BICHI r0, r0, r3 BICHI r0, r0, r3
ADDHI r0, r0, r1
STR r2, [r0, #-4] STR r2, [r0, #-4]
LDR r3, mempool_base_phys LDR r3, mempool_base_phys
SUB lr, r0, r1 SUB lr, r0, r1
...@@ -139,13 +156,19 @@ GotAllocedNoOSHeap7 ...@@ -139,13 +156,19 @@ GotAllocedNoOSHeap7
DREG r1, ", physical address = " DREG r1, ", physical address = "
] ]
ADD sp, sp, #4 ADD sp, sp, #4
Pull "r2-r4,pc" Pull "r2-r5,pc"
BadAlign
; Mimic error that's generated if the heap isn't big enough
Pull "r1-r5,lr"
ADRL r0, ErrorBlock_ChDynamNotAllMoved
B copy_error_zero
RAMFree RAMFree
Push "r1,r2,lr" Push "r1,r2,lr"
; If OS_Heap 7 is supported, all pointers are to heap blocks ; If OS_Heap 8 is supported, all pointers are to heap blocks
; Else the word before the pointer points to the heap block ; Else the word before the pointer points to the heap block
LDRB r2, osheap7_supported LDRB r2, osheap8_supported
CMP r2, #0 CMP r2, #0
LDREQ r2, [r0, #-4] LDREQ r2, [r0, #-4]
MOVNE r2, r0 MOVNE r2, r0
...@@ -171,42 +194,76 @@ InitDA ...@@ -171,42 +194,76 @@ InitDA
MOVVC r6, #0 MOVVC r6, #0
MOVVC r7, #0 MOVVC r7, #0
SWIVC XMessageTrans_Lookup SWIVC XMessageTrans_Lookup
MOVVC r0, #0 BVS %FT19
STRVCB r0, [r2, r3] MOV r0, #0
MOVVC r8, r2 STRB r0, [r2, r3]
MOVVC r0, #DAReason_Create MOV r8, r2
MOVVC r1, #-1
STRVC r1, mempool_base_ppn MOV r1, #32*1024*1024 ; Try for 32M, 4M aligned
MOVVC r2, #0 MOV r2, #22
MOVVC r3, #-1 02 LDR r0, =OSMemReason_RecommendPage+256 ; Request DMAable memory
MOVVC r4, #2_00100010 ; SVC only, B, ~C, draggable SWI XOS_Memory
ORRVC r4, r4, #&100 ; requires specific physical pages BVC %FT30
MOVVC r5, #32*1024*1024 MOV r1, r1, LSR #1 ; If we can't get it, halve both
ADRVC r6, DynAreaHandler SUB r2, r2, #1 ; until down to 32K, 4K aligned
MOVVC r7, wp TST r1, #16*1024 ; preserve V flag in loop test
SWIVC XOS_DynamicArea BEQ %BT02
19
STRVS r0, [sp]
Pull "r0-r8,pc",VS
30
[ DebugMemory
DREG r3, "PPN suggested ",,Integer
]
STR r1, mempool_max_size
STR r2, mempool_alignment
STR r3, mempool_base_ppn
MOV r5, r1
; See if we can reserve the physical pages, to ensure they're available
; when we need them
MOV r0, #OSMemReason_ReservePages
MOV r1, r3
MOV r2, r5, LSR #12
SWI XOS_Memory
MOVVS r0, #0
MOVVC r0, #1
STRB r0, osmemory23_supported
; Get physical addr of memory
MOV r0, #(2_100001:SHL:8) + OSMemReason_Convert
ADR r1, mempool_base_ppn
MOV r2, #1
SWI XOS_Memory
BVS %FT90
[ DebugMemory
LDR r0, mempool_base_phys
DREG r0, "Physical address "
]
MOV r0, #DAReason_Create
MOV r1, #-1
MOV r2, #4096
MOV r3, #-1
LDR r4, =2+DynAreaFlags_NotCacheable+DynAreaFlags_NeedsSpecificPages ; SVC only, B, ~C, draggable, requires specific physical pages
ADR r6, DynAreaHandler
MOV r7, wp
SWI XOS_DynamicArea
BVS %FT90
[ DebugMemory [ DebugMemory
BVS %FT01
DREG r1, "Dynamic area ",,Integer DREG r1, "Dynamic area ",,Integer
DREG r3, "Logical address " DREG r3, "Logical address "
01
] ]
STRVS r0, [sp] STR r1, mempool_da_number
Pull "r0-r8,pc",VS
20 STR r1, mempool_da_number
STR r3, mempool_base_log STR r3, mempool_base_log
STR r3, mempool_free ; Init the heap
; Grow by one page so we can init the heap MOV r0, #HeapReason_Init
; (can't do the initial grow during DA create since the pre-grow handler needs to know the logical base) MOV r1, r3
SWI XOS_ReadMemMapInfo MOV r3, r2
MOVVC r1, r0 SWI XOS_Heap
LDRVC r0, mempool_da_number
SWIVC XOS_ChangeDynamicArea
MOVVC r0, #HeapReason_Init
MOVVC r3, r1
LDRVC r1, mempool_base_log
SWIVC XOS_Heap
Pull "r0-r8,pc",VC Pull "r0-r8,pc",VC
90
; error case ; error case
STR r0,[sp] STR r0,[sp]
BL KillDA BL KillDA
...@@ -214,7 +271,18 @@ InitDA ...@@ -214,7 +271,18 @@ InitDA
Pull "r0-r8,pc" Pull "r0-r8,pc"
KillDA KillDA
Push "r0-r1,lr" Push "r0-r2,lr"
; Release the pages we reserved
LDRB r0, osmemory23_supported
CMP r0, #0
MOVNE r0, #0
STRNEB r0, osmemory23_supported
LDRNE r0, =OSMemReason_ReservePages+256
LDRNE r1, mempool_base_ppn
LDRNE r2, mempool_max_size
MOVNE r2, r2, LSR #12
SWINE XOS_Memory
; Kill the DA
MOV r0, #DAReason_Remove MOV r0, #DAReason_Remove
LDR r1, mempool_da_number LDR r1, mempool_da_number
CMP r1, #0 CMP r1, #0
...@@ -228,7 +296,7 @@ KillDA ...@@ -228,7 +296,7 @@ KillDA
STR r1, mempool_da_number STR r1, mempool_da_number
STR r1, mempool_base_log STR r1, mempool_base_log
STRVS r0, [sp] STRVS r0, [sp]
Pull "r0-r1,pc" Pull "r0-r2,pc"
Token_DAName Token_DAName
= "DAName", 0 = "DAName", 0
...@@ -255,53 +323,12 @@ UnknownHandlerError ...@@ -255,53 +323,12 @@ UnknownHandlerError
; R4 = current size (bytes) ; R4 = current size (bytes)
; R5 = page size ; R5 = page size
; ;
; exit with V clear, all preserved ; exit with V clear, R0=0 or DAHandler_RESV
PreGrow Entry "r0-r3" PreGrow Entry "r1-r3"
LDR r3, mempool_base_ppn LDR r3, mempool_base_ppn
CMP r3, #-1 MOV lr, #0
BNE %FT05
MOV r1, #32*1024*1024 ; Try for 32M, 4M aligned
MOV r2, #22
02 MOV r0, #OSMemReason_RecommendPage
SWI XOS_Memory
BVC %FT03
MOV r1, r1, LSR #1 ; If we can't get it, halve both
SUB r2, r2, #1 ; until down to 32K, 4K aligned
TST r1, #16*1024 ; preserve V flag in loop test
BEQ %BT02
B %FT99
03
[ DebugMemory
DREG r3, "PPN suggested ",,Integer
]
; Skip the first few pages of the region, to ensure physical alignment and logical alignment match
; (all our allocation functions work by aligning based around logical addresses, when really what the client wants is physically aligned memory)
MOV r0, #1
MOV r2, r0, LSL r2
SUB r2, r2, #1
LDR r0, mempool_base_log
AND r0, r0, r2
ADD r3, r3, r0, LSR #12
[ DebugMemory
DREG r3, "PPN aligned ",,Integer
]
STR r3, mempool_base_ppn
MOV r0, #(2_100001:SHL:8) + OSMemReason_Convert
ADR r1, mempool_base_ppn
MOV r2, #1
SWI XOS_Memory
BVS %FT99
[ DebugMemory
LDR r0, mempool_base_phys
DREG r0, "Physical address "
]
LDMFD sp, {r0-r2} ; recover input parameters
05 MOV lr, #0
[ DebugMemory [ DebugMemory
DREG r4, "Current size ",cc DREG r4, "Current size ",cc
DREG r5, ", page size " DREG r5, ", page size "
...@@ -319,7 +346,9 @@ PreGrow Entry "r0-r3" ...@@ -319,7 +346,9 @@ PreGrow Entry "r0-r3"
ADDNE r3, r3, #1 ADDNE r3, r3, #1
BNE %BT20 BNE %BT20
99 STRVS r0, [sp] LDRB r0, osmemory23_supported
CMP r0, #0
LDRNE r0, =DAHandler_RESV ; Allow use of the pages we reserved
EXIT EXIT
PostGrow PostGrow
......
...@@ -56,21 +56,23 @@ ModuleFlags ...@@ -56,21 +56,23 @@ ModuleFlags
Word pci_handle_table_size Word pci_handle_table_size
Word pci_handles Word pci_handles
Word pci_mem_to_phys_offset ; From HAL_PCIAddresses Word pci_mem_to_phys_offset, 2 ; From HAL_PCIAddresses
Word pci_mem_lowest Word pci_mem_lowest
Word pci_mem_highest Word pci_mem_highest
Word pci_io_to_phys_offset Word pci_io_to_phys_offset, 2
Word pci_io_lowest Word pci_io_lowest
Word pci_io_highest Word pci_io_highest
Word ram_to_pci_mem_offset Word ram_to_pci_mem_offset, 2
Word mempool_da_number Word mempool_da_number
Word mempool_base_ppn ; this is a page block Word mempool_base_ppn ; this is a page block
Word mempool_base_log Word mempool_base_log
Word mempool_base_phys Word mempool_base_phys
Word mempool_base_pci Word mempool_base_pci
Word mempool_free Word mempool_alignment
Byte osheap7_supported Word mempool_max_size
Byte osheap8_supported
Byte osmemory23_supported
Byte pcibus_supported Byte pcibus_supported
AlignSpace AlignSpace
Byte name_buffer, 128 Byte name_buffer, 128
...@@ -121,17 +123,17 @@ InitModule ...@@ -121,17 +123,17 @@ InitModule
STRPL r0, [r12, r3] STRPL r0, [r12, r3]
BPL %BT10 BPL %BT10
; Check if OS_Heap 7 (get area aligned) is supported ; Check if OS_Heap 8 (get area aligned relative to R5) is supported
; We'll do a dummy call with a bad heap block and see what error we get ; We'll do a dummy call with a bad heap block and see what error we get
; back (Assumes bad reason codes will always be checked first!) ; back (Assumes bad reason codes will always be checked first!)
MOV r0, #HeapReason_GetAligned MOV r0, #HeapReason_GetSkewAligned
MOV r1, r12 ; Valid address but not a heap MOV r1, r12 ; Valid address but not a heap
SWI XOS_Heap SWI XOS_Heap
LDRVS r0, [r0] LDRVS r0, [r0]
TEQVS r0, #ErrorNumber_HeapBadReason ; EQ if unsupported TEQVS r0, #ErrorNumber_HeapBadReason ; EQ if unsupported
TEQVC r1, r1 ; EQ if no error returned (definitely a bad sign) TEQVC r1, r1 ; EQ if no error returned (definitely a bad sign)
MOVNE r0, #1 MOVNE r0, #1
STRNEB r0, osheap7_supported STRNEB r0, osheap8_supported
BL SetUpHAL BL SetUpHAL
; If we get an error back there is no PCI. But do not give up, ; If we get an error back there is no PCI. But do not give up,
...@@ -173,10 +175,19 @@ SetUpHAL ROUT ...@@ -173,10 +175,19 @@ SetUpHAL ROUT
BVS %FT99 BVS %FT99
ADR a1, pci_mem_to_phys_offset ADR a1, pci_mem_to_phys_offset
MOV a2, #7*4 MOV a2, #10*4
MOV r8, #OSHW_CallHAL MOV r8, #OSHW_CallHAL
MOV r9, #EntryNo_HAL_PCIAddresses MOV r9, #EntryNo_HAL_PCIAddresses
SWI XOS_Hardware SWI XOS_Hardware
TEQ a1, #7*4 ; Old HAL_PCIAddresses layout?
Push "r4-r7", EQ
ADREQ lr, pci_mem_to_phys_offset
LDMEQIA lr, {r0, r2-r4, r6-r8} ; Read in old layout
MOVEQ r1, #0
MOVEQ r5, #0
MOVEQ r9, #0
STMEQIA lr, {r0-r9} ; Write out in new layout with upper words 0
Pull "r4-r7", EQ
99 99
Pull "r8,r9,pc" Pull "r8,r9,pc"
......