Commit 462f20a7 authored by Robert Sprowson's avatar Robert Sprowson Committed by ROOL
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Allow mappings from PCI address space to 64b I/O memory

Extend the previously 32b offsets from PCI to ARM (physical) addresses as retrieved with HAL_PCIAddresses to instead by 64b offsets. After having applied the offset, choose the 64b versions of OS_Memory to map them in.
No SWI interfaces are harmed in the making of this change.
parent 9b92bcef
......@@ -246,14 +246,17 @@ IORead ROUT
LDRB r10, pcibus_supported
TEQ r10, #0
BEQ BadWithNoBus
LDR r11, pci_io_to_phys_offset
LDR r10, pci_io_to_phys_offset + 0
LDR r11, pci_io_to_phys_offset + 4
TEQ r2, #1
TEQNE r2, #2
TEQNE r2, #4
BNE BadAccessSize
Push "r0,r2,r3,lr"
ADD r1, r0, r11
MOV r0, #OSMemReason_AccessPhysAddr
ADDS r1, r10, r0
ADCS r2, r11, #0
MOVNE r0, #OSMemReason_AccessPhysAddr64
MOVEQ r0, #OSMemReason_AccessPhysAddr
SWI XOS_Memory ; r2 -> logical addr, r3 = old state
LDR r11, [sp, #4]
BVS %FT99
......@@ -276,14 +279,17 @@ IOWrite ROUT
LDRB r10, pcibus_supported
TEQ r10, #0
BEQ BadWithNoBus
LDR r11, pci_io_to_phys_offset
LDR r10, pci_io_to_phys_offset + 0
LDR r11, pci_io_to_phys_offset + 4
TEQ r2, #1
TEQNE r2, #2
TEQNE r2, #4
BNE BadAccessSize
Push "r0-r3,lr"
ADD r1, r0, r11
MOV r0, #OSMemReason_AccessPhysAddr
ADDS r1, r10, r0
ADCS r2, r11, #0
MOVNE r0, #OSMemReason_AccessPhysAddr64
MOVEQ r0, #OSMemReason_AccessPhysAddr
SWI XOS_Memory ; r2 -> logical addr, r3 = old state
LDMIB sp, {r1, r11}
BVS %FT99
......@@ -304,11 +310,14 @@ MemoryRead ROUT
LDRB r10, pcibus_supported
TEQ r10, #0
BEQ BadWithNoBus
LDR r11, pci_mem_to_phys_offset
LDR r10, pci_mem_to_phys_offset + 0
LDR r11, pci_mem_to_phys_offset + 4
Push "r0-r3,lr"
BIC r1, r0, #3 ; force it to be word aligned
ADD r1, r11, r1
MOV r0, #OSMemReason_AccessPhysAddr
ADDS r1, r10, r1
ADCS r2, r11, #0
MOVNE r0, #OSMemReason_AccessPhysAddr64
MOVEQ r0, #OSMemReason_AccessPhysAddr
SWI XOS_Memory ; r2 -> logical addr, r3 = old state
LDR r11, [sp, #8] ; points to destination buffer
LDR r12, [sp, #4] ; the length to do
......@@ -319,22 +328,20 @@ MemoryRead ROUT
STR r14, [r11], #4
TEQ r11, r12
BNE %BT80
MOV r0, #OSMemReason_ReleasePhysAddr
MOV r1, r3
SWI XOS_Memory ; release
BVS %FT99
Pull "r0-r3,pc"
B %FT98
MemoryWrite
LDRB r10, pcibus_supported
TEQ r10, #0
BEQ BadWithNoBus
LDR r11, pci_mem_to_phys_offset
LDR r10, pci_mem_to_phys_offset + 0
LDR r11, pci_mem_to_phys_offset + 4
Push "r0-r3,lr"
BIC r1, r0, #3 ; force it to be word aligned
ADD r1, r11, r1
MOV r0, #OSMemReason_AccessPhysAddr
ADDS r1, r10, r1
ADCS r2, r11, #0
MOVNE r0, #OSMemReason_AccessPhysAddr64
MOVEQ r0, #OSMemReason_AccessPhysAddr
SWI XOS_Memory ; r2 -> logical addr, r3 = old state
LDR r11, [sp, #8] ; points to source buffer
LDR r12, [sp, #4] ; the length to do
......@@ -345,7 +352,7 @@ MemoryWrite
STR r14, [r2]
TEQ r11, r12
BNE %BT90
98
MOV r0, #OSMemReason_ReleasePhysAddr
MOV r1, r3
SWI XOS_Memory ; release
......@@ -457,12 +464,17 @@ HardwareAddress
TST r10, #1:SHL:31 ; Query only
BNE %FT40
LDRB r0, [r11, #PCIAddress_Flags]
Push "r1"
Push "r1, r2"
MOV r3, r2
TST r0, #Address_IO
LDRNE lr, pci_io_to_phys_offset
LDREQ lr, pci_mem_to_phys_offset
ADD r1, r1, lr
MOV r0, #OSMemReason_MapIOPermanent
ADRNE r2, pci_io_to_phys_offset
ADREQ r2, pci_mem_to_phys_offset
LDMIA r2, {r2, lr}
ADDS r1, r2, r1
ADCS r2, lr, #0
MOVNE r0, #OSMemReason_MapIO64Permanent
MOVEQ r0, #OSMemReason_MapIOPermanent
MOVEQ r2, r3
AND lr, r10, #&1F0 ; B+C+policy bits
ORR r0, r0, lr, LSL #4
TST r10, #1:SHL:9 ; Access privileges given
......@@ -470,7 +482,7 @@ HardwareAddress
ANDNE lr, r10, #2_1111
ORRNE r0, r0, lr, LSL #24
SWI XOS_Memory
Pull "r1"
Pull "r1, r2"
MOVVC r4, r3
40 LDRVCB r0, [r11, #PCIAddress_Flags]
90 ADD sp, sp, #8
......@@ -490,18 +502,23 @@ LogicalAddress
LDRB r10, pcibus_supported
TEQ r10, #0
BEQ BadWithNoBus
Push "r0,r1,r3,lr"
Push "r0-r3,lr"
MOV r3, r2
TST r0, #1:SHL:30
LDRNE lr, pci_io_to_phys_offset
LDREQ lr, pci_mem_to_phys_offset
ADD r1, r1, lr
ADRNE r2, pci_io_to_phys_offset
ADREQ r2, pci_mem_to_phys_offset
LDMIA r2, {r2, lr}
ADDS r1, r2, r1
ADCS r2, lr, #0
AND r0, r0, #&1F0 ; B+C+policy bits
MOV r0, r0, LSL #4
ORR r0, r0, #OSMemReason_MapIOPermanent
ORRNE r0, r0, #OSMemReason_MapIO64Permanent
ORREQ r0, r0, #OSMemReason_MapIOPermanent
MOVEQ r2, r3
SWI XOS_Memory
STRVS r0, [sp]
MOVVC r4, r3
Pull "r0,r1,r3,pc"
Pull "r0-r3,pc"
; ****************************************************************************
;
......@@ -537,6 +554,8 @@ LogicalAddress
; Bit 12 ==> Ethernet address (low 32 bits)
; Bit 13 ==> Ethernet address (high 16 bits)
; Bit 14 ==> Logical number of the primary DMA channel
; Bit 15 ==> Number of BARs
; Bit 16 ==> Pointer to vendor (0 for none)
ReadInfo ROUT
Push "r0-r6, lr"
......
......@@ -56,13 +56,13 @@ ModuleFlags
Word pci_handle_table_size
Word pci_handles
Word pci_mem_to_phys_offset ; From HAL_PCIAddresses
Word pci_mem_to_phys_offset, 2 ; From HAL_PCIAddresses
Word pci_mem_lowest
Word pci_mem_highest
Word pci_io_to_phys_offset
Word pci_io_to_phys_offset, 2
Word pci_io_lowest
Word pci_io_highest
Word ram_to_pci_mem_offset
Word ram_to_pci_mem_offset, 2
Word mempool_da_number
Word mempool_base_ppn ; this is a page block
......@@ -175,7 +175,7 @@ SetUpHAL ROUT
BVS %FT99
ADR a1, pci_mem_to_phys_offset
MOV a2, #7*4
MOV a2, #10*4
MOV r8, #OSHW_CallHAL
MOV r9, #EntryNo_HAL_PCIAddresses
SWI XOS_Hardware
......
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