Commit e74d1d9a authored by Ben Avison's avatar Ben Avison
Browse files

Folded in HAL branch.

Version 0.16. Tagged as 'DMA-0_16'
parent 99697a06
Description Logical Physical (IOMD) Physical (IOMD2) DMAReq (7200) DMAReq (9200)
Expansion card 0, DMA line 0 &000 2 2 14 or 15
Expansion card 0, DMA line 1 &001 14 or 15
Expansion card 1, DMA line 0 &010 3 3 14 or 15
Expansion card 1, DMA line 1 &011 14 or 15
Expansion card 2, DMA line 0 &020 14 or 15
Expansion card 2, DMA line 1 &021 14 or 15
Expansion card 3, DMA line 0 &030 14 or 15
Expansion card 3, DMA line 1 &031 14 or 15
Expansion card 4, DMA line 0 &040 14 or 15
Expansion card 4, DMA line 1 &041 14 or 15
Expansion card 5, DMA line 0 &050 14 or 15
Expansion card 5, DMA line 1 &051 14 or 15
Expansion card 6, DMA line 0 &060 14 or 15
Expansion card 6, DMA line 1 &061 14 or 15
Expansion card 7, DMA line 0 &070 14 or 15
Expansion card 7, DMA line 1 &071 14 or 15
On-board SCSI &100
On-board floppy &101 1 0
Parallel &102 1 5
Sound 1 &103 4 23(RX) / 24(TX) &8004C080 1
Sound 0 &104 5 1(RX) / 2(TX) &80040008 burst half-word 0
Network card &105 0
IDE 0 &106 7 15
IDE 1 &107 6
Sound 2 &108 1 2
Sound 3 &109 4 3
PCI 0 &10A
PCI 1 &10B
Modem 0 &200 3(RX) / 4(TX) &8004000C burst half-word
Modem 1 &201 25(RX) / 26(TX) &8004C0C0
Modem 2 &202
Modem 3 &203
Serial 0 &210 11(RX) / 12(TX) &80044000 7(RX) / 4(TX)
Serial 1 &211 13(RX) / 14(TX) &80045000 8(RX) / 5(TX)
Serial 2 &212 5(RX) / 6(TX) &80041008 9(RX) / 6(TX)
Serial 3 &213 9(RX) / 10(TX) &8004206C 12(RX) / 10(TX)
Serial 4 &214 13(RX) / 11(TX)
Serial 5 &215
Serial 6 &216
Serial 7 &217
USB 0 &220 7(RX) / 8(TX) &8004B070(RX)/80(TX)
USB 1 &221
IrDA 0 &230 15(RX) / 16(TX) &80046010 non-burst word
IrDA 1 &231
GPIO 0 &240 19(RX) / 20(TX) &80010010 burst
GPIO 1 &241
MultiMediaCard 0 &250 21(RX) / 22(TX) &8004A034
MultiMediaCard 1 &251
Memory-to-memory 0 &FF0 17(RX) / 18(TX) &80030010 burst Not synchronised
Memory-to-memory 1 &FF1
DMAManager SWIs
---------------
SWI DMA_RegisterChannel extended as follows:
R0 bits 0-3 = post-transfer channel delay
R0 bit 4 set => disable burst transfers
R0 bit 5 set => disable DMA request synchronisation to clock
R6 = peripheral read/receive physical address, or -1 to disallow reads
R7 = peripheral write/transmit physical address, or -1 to disallow writes
(R6,R7 ignored for IOMD implementations and memory-to-memory DMA, but
otherwise required for the 7200 and 9200)
SWI DMA_ExamineTransfer may not be able to give an accurate byte count for
some DMA controllers; however the byte count returned is guaranteed not to
exceed the true count. If you need a guaranteed accurate value, you must call
it between DMA_SuspendTransfer and DMA_ResumeTransfer. (This has always been
the case.)
Future enhancement:
> SWIs DMA_ClaimChannel and DMA_ReleaseChannel reinstated, but modified so
> as to take the logical channel as a parameter and not returning any
> information about the physical channel. These allow a logical channel to
> temporarily gain sole use of a physical channel, typically to guarantee
> reception of incoming data.
Two types of devices (see Kernel.Docs.HAL.NewAPI) are defined: the DMA
controller, and the DMA (physical) channel.
DMA controller device
---------------------
struct dmacontroller
{
/* Public interface */
struct device dev;
uint32_t (*Features)(struct dmacontroller *);
__value_in_regs struct { struct dmachannel **channel; uint32_t count; }
(*Enumerate)(struct dmacontroller *);
struct dmachannel *(*Allocate)(struct dmacontroller *, uint32_t channel);
void (*Deallocate)(struct dmacontroller *, uint32_t channel);
}
dev.type
dev.id
dev.location
dev.version
dev.description
dev.address
dev.Activate
dev.Deactivate
dev.Reset
dev.Sleep
dev.devicenumber
dev.TestIRQ
Standard functions as defined in Docs.HAL.NewAPI.
Type = &302.
Address is not used.
Controllers are activated/deactivated on module initialisation/finalisation.
Interrupts are ignored - provide them using the DMA channel device instead.
Features
Returns a flags word indicating the capabilities of the controller.
Currently no bits defined, all bits should be zero.
Enumerate
Returns a static list of available physical DMA channel devices.
Allocate
Returns pointer to the physical DMA channel struct to associate with the
given logical DMA channel. If the hardware requires a particular logical-
physical mapping, this will be obeyed; otherwise one will be allocated at
the whim of the software (typically: physical channels grouped according to
priority of logical channel, then within each group logical channels are
allocated on a one-to-one mapping until no physical channels remain,
after which logical channels are arbitrarily doubled up).
Return value NULL => this logical channel not supported on this controller
Recommended DMA priorities:
High: sound DMA
Medium: other device DMA
Low: memory-to-memory DMA
Deallocate
The partner of Allocate, this lets the device know that a particular
logical channel is no longer being used.
DMA channel device - buffer type
--------------------------------
struct dmachannel
{
/* Public interface */
struct device dev;
uint32_t (*Features)(struct dmachannel *);
dmacontroller *Controller;
void (*Abort)(struct device *);
void (*SetOptions)(struct dmachannel *, uint32_t flags, uint32_t address);
void (*SetCurrentTransfer)(struct dmachannel *, uint32_t address,
uint32_t length, uint32_t flags);
void (*SetNextTransfer)(struct dmachannel *, uint32_t address,
uint32_t length, uint32_t flags);
__value_in_regs struct { uint32_t address; uint32_t length; }
(*TransferState)(struct dmachannel *);
void (*IRQClear)(struct dmachannel *);
uint32_t (*Status)(struct dmachannel *);
void (*SetCurrentTransfer2)(struct dmachannel *, uint32_t srcaddress,
uint32_t dstaddress, uint32_t length, uint32_t flags);
void (*SetNextTransfer2)(struct dmachannel *, uint32_t srcaddress,
uint32_t dstaddress, uint32_t length, uint32_t flags);
__value_in_regs struct { uint32_t srcaddress; uint32_t dstaddress;
uint32_t length; } (*TransferState2)(struct dmachannel *);
}
dev.type
dev.id
dev.location
dev.version
dev.description
dev.address
dev.Activate
dev.Deactivate
dev.Reset
dev.Sleep
dev.devicenumber
dev.TestIRQ
Standard functions as defined in Docs.HAL.NewAPI.
Type = &303.
Address is not used.
Channels are activated/deactivated around each transfer.
dev.Activate enables this physical DMA channel, so that it can generate
interrupts (typically this involves unmasking the DMA request line and
unmasking a bit in an interrupt control register).
dev.Deactivate must block until the transfer on this channel can safely be
interrupted (due to Service_PagesUnsafe or SWI DMA_SuspendTransfer),
then disable DMA at the DMA request line and interrupt generation levels.
After it returns, the values returned from TransferState and Status must
reflect the true state of the hardware - ie they must be suitable to use for
resumption of the transfer using SetCurrentTransfer.
dev.Reset is called by the DMAManager between transfers (as well as by the
kernel on software-initiated resets). After this call, Status must report an
over/underrun condition.
Features
Returns a flag word:
bit 0 set => DMA transfers cannot be paused, so if *any* of the scatter
list entries is for an unsafe page when the transfer is
activated, then the whole transfer must be delayed
other bits reserved, should be zero
Controller
A pointer to this channel's DMA controller device.
Abort
This should be considered a "forced" version of dev.Deactivate, and is only
used for SWI DMA_TerminateTransfer. The call must not block, but the values
subsequently returned from TransferState and Status are allowed to report
inaccurate results, providing they underestimate the progress of the
transfer.
SetOptions
|flags| sets the following aspects of the next transfer on this channel:
bit 0 set => memory to device, clear => device to memory
(ignored for any memory-to-memory channel)
bits 1-5 => transfer unit width, typically 1, 2 or 4 bytes
(16 bytes can also be used for IOMD)
bits 6-8 => cycle speed, on an arbitrary scale from 0-7
(0-3 maps to A-D cycles on IOMD)
bits 9-12 => minimum delay required after a DMA transfer before the same
physical channel is reused (required for 7200 and 9200)
bit 13 set => disable burst transfers for this channel
bit 14 set => bypass synchronisation to clock before initiating transfer
(for synchronous peripherals - currently 7200 only)
other bits reserved, value must be ignored
|address| sets the physical address of the peripheral to DMA to/from
(should be ignored by memory-to-memory channels)
SetCurrentTransfer
This sets up the first transfer to be executed for this channel
address = physical address to start transfer from
length = number of bytes to transfer
flags bit 0 set => stop and raise the TC signal when this transfer completes
(mandatory if the DMA controller has no interrupt of
its own)
address and length should be multiples of the transfer unit size, and must
not cross a page boundary
SetNextTransfer
This sets up the next transfer to be executed for this channel, using similar
parameters. This will only be called for double-buffered channels.
TransferState
This reads the progress of the current transfer on this channel.
If the DMA controller will not report accurate progress, report values
corresponding to a pessimistic amount of progress.
IRQClear
Clears the interrupt for this physical DMA channel (unless some other action
carried out during or since TestIRQ has already done so).
Status
Returns status bits for the current channel:
bit 0 set => there are no transfers programmed but not yet started
(for a double-buffered controller, this is set when interrupting
or for a single-buffered controller, this is always set)
bit 1 set => channel has not yet been used, or is in over/underrun state
(set on every interrupt for single-buffered DMA controllers)
bit 2 set => channel entered over/underrun state before last call to
SetNextTransfer had effect (devices may determine this by
monitoring any handle they may have on the physical double
buffers, or failing this by calculating the final value of the
current pointer of the current buffer, and comparing it to what
would be expected from the last time the next buffer was
programmed - but note that this latter algorithm will fail if a
circular transfer from a single-entry scatter list is in use)
so the DMA manager needs to program the same data again, but
this time using SetCurrentTransfer. This bit must be clear if
the last transfer was programmed using SetCurrentTransfer, or if
bit 1 is clear.
SetCurrentTransfer2 / SetNextTransfer2 / TransferState2
are same as above but with two address arguments and one length argument. For
use in memory-to-memory transfers only.
......@@ -28,6 +28,7 @@
COMPONENT = DMAManager
TARGET = DMA
HEADER1 = DMA
HEADER2 = DMADevice
ROM_SOURCE = GetAll.s
include StdTools
......
| Copyright 2002 Tematic Ltd
|
| Licensed under the Apache License, Version 2.0 (the "License");
| you may not use this file except in compliance with the License.
| You may obtain a copy of the License at
|
| http://www.apache.org/licenses/LICENSE-2.0
|
| Unless required by applicable law or agreed to in writing, software
| distributed under the License is distributed on an "AS IS" BASIS,
| WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
| See the License for the specific language governing permissions and
| limitations under the License.
|
Dir <Obey$Dir>
amu_machine export
| Copyright 2002 Tematic Ltd
|
| Licensed under the Apache License, Version 2.0 (the "License");
| you may not use this file except in compliance with the License.
| You may obtain a copy of the License at
|
| http://www.apache.org/licenses/LICENSE-2.0
|
| Unless required by applicable law or agreed to in writing, software
| distributed under the License is distributed on an "AS IS" BASIS,
| WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
| See the License for the specific language governing permissions and
| limitations under the License.
|
Dir <Obey$Dir>
amu_machine gpa_debug THROWBACK=-throwback
| Copyright 2002 Tematic Ltd
|
| Licensed under the Apache License, Version 2.0 (the "License");
| you may not use this file except in compliance with the License.
| You may obtain a copy of the License at
|
| http://www.apache.org/licenses/LICENSE-2.0
|
| Unless required by applicable law or agreed to in writing, software
| distributed under the License is distributed on an "AS IS" BASIS,
| WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
| See the License for the specific language governing permissions and
| limitations under the License.
|
Dir <Obey$Dir>
amu_machine standalone THROWBACK=-throwback
No preview for this file type
;
; This file is automatically maintained by srccommit, do not edit manually.
; Last processed by srccommit version: 1.68.
;
GBLS Module_MajorVersion
GBLA Module_Version
GBLS Module_MinorVersion
GBLS Module_Date
GBLS Module_FullVersion
GBLS Module_ApplicationDate2
GBLS Module_ApplicationDate4
GBLS Module_ApplicationDate
GBLS Module_HelpVersion
GBLS Module_ComponentName
GBLS Module_ComponentPath
Module_MajorVersion SETS "0.15"
Module_Version SETA 15
Module_MajorVersion SETS "0.16"
Module_Version SETA 16
Module_MinorVersion SETS ""
Module_Date SETS "11 Apr 2001"
Module_ApplicationDate2 SETS "11-Apr-01"
Module_ApplicationDate4 SETS "11-Apr-2001"
Module_Date SETS "13 Dec 2002"
Module_ApplicationDate SETS "13-Dec-02"
Module_ComponentName SETS "DMA"
Module_ComponentPath SETS "RiscOS/Sources/HWSupport/DMA"
Module_FullVersion SETS "0.15"
Module_HelpVersion SETS "0.15 (11 Apr 2001)"
Module_FullVersion SETS "0.16"
Module_HelpVersion SETS "0.16 (13 Dec 2002)"
END
/* (0.15)
/* (0.16)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.68.
*
*/
#define Module_MajorVersion_CMHG 0.15
#define Module_MajorVersion_CMHG 0.16
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 11 Apr 2001
#define Module_Date_CMHG 13 Dec 2002
#define Module_MajorVersion "0.15"
#define Module_Version 15
#define Module_MajorVersion "0.16"
#define Module_Version 16
#define Module_MinorVersion ""
#define Module_Date "11 Apr 2001"
#define Module_Date "13 Dec 2002"
#define Module_ApplicationDate2 "11-Apr-01"
#define Module_ApplicationDate4 "11-Apr-2001"
#define Module_ApplicationDate "13-Dec-02"
#define Module_ComponentName "DMA"
#define Module_ComponentPath "RiscOS/Sources/HWSupport/DMA"
#define Module_FullVersion "0.15"
#define Module_HelpVersion "0.15 (11 Apr 2001)"
#define Module_FullVersion "0.16"
#define Module_HelpVersion "0.16 (13 Dec 2002)"
#define Module_LibraryVersionInfo "0:16"
......@@ -41,7 +41,59 @@ SWIClass SETS DMAManagerSWI_Name
AddSWI ExamineTransfer
; Reason codes:
; Logical DMA channels
DMALC_Podule0Line0 * &000
DMALC_Podule0Line1 * &001
DMALC_Podule1Line0 * &010
DMALC_Podule1Line1 * &011
DMALC_Podule2Line0 * &020
DMALC_Podule2Line1 * &021
DMALC_Podule3Line0 * &030
DMALC_Podule3Line1 * &031
DMALC_Podule4Line0 * &040
DMALC_Podule4Line1 * &041
DMALC_Podule5Line0 * &050
DMALC_Podule5Line1 * &051
DMALC_Podule6Line0 * &060
DMALC_Podule6Line1 * &061
DMALC_Podule7Line0 * &070
DMALC_Podule7Line1 * &071
DMALC_SCSI * &100
DMALC_Floppy * &101
DMALC_Parallel * &102
DMALC_Sound1 * &103
DMALC_Sound0 * &104
DMALC_Network * &105
DMALC_IDE0 * &106
DMALC_IDE1 * &107
DMALC_Sound2 * &108
DMALC_Sound3 * &109
DMALC_PCI0 * &10A
DMALC_PCI1 * &10B
DMALC_Modem0 * &200
DMALC_Modem1 * &201
DMALC_Modem2 * &202
DMALC_Modem3 * &203
DMALC_Serial0 * &210
DMALC_Serial1 * &211
DMALC_Serial2 * &212
DMALC_Serial3 * &213
DMALC_Serial4 * &214
DMALC_Serial5 * &215
DMALC_Serial6 * &216
DMALC_Serial7 * &217
DMALC_USB0 * &220
DMALC_USB1 * &221
DMALC_IrDA0 * &230
DMALC_IrDA1 * &231
DMALC_GPIO0 * &240
DMALC_GPIO1 * &241
DMALC_MMC0 * &250
DMALC_MMC1 * &251
DMALC_M2M0 * &FF0
DMALC_M2M1 * &FF1
OPT OldOpt
END
; Copyright 2002 Tematic Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
; Public interface (ie interface to DMAManager) of DMA HAL devices
GET hdr:HALDevice
OldOpt SETA {OPT}
OPT OptNoList+OptNoP1List
[ :LNOT: :DEF: Included_Hdr_DMADevice
GBLL Included_Hdr_DMADevice
Included_Hdr_DMADevice SETL {TRUE}
; Device for each DMA controller
^ 0
# HALDeviceSize
HALDevice_DMACFeatures # 4
HALDevice_DMACEnumerate # 4
HALDevice_DMACAllocate # 4
HALDevice_DMACDeallocate # 4
HALDevice_DMAC_Size * :INDEX: @
; Device for each physical DMA channel (buffer type)
^ 0
# HALDeviceSize
HALDevice_DMAFeatures # 4
HALDevice_DMAController # 4
HALDevice_DMAAbort # 4
HALDevice_DMASetOptions # 4
HALDevice_DMASetCurrentTransfer # 4
HALDevice_DMASetNextTransfer # 4
HALDevice_DMATransferState # 4
HALDevice_DMAIRQClear # 4
HALDevice_DMAStatus # 4
HALDevice_DMASetCurrentTransfer2 # 4
HALDevice_DMASetNextTransfer2 # 4
HALDevice_DMATransferState2 # 4
HALDevice_DMA_Size * :INDEX: @
DMAFeaturesFlag_CantSuspend * 1 :SHL: 0 ; don't activate transfer until all of the scatter list is on safe pages
DMASetOptionsFlag_Write * 1 :SHL: 0
DMASetOptionsShift_Width * 1
DMASetOptionsMask_Width * 31 :SHL: DMASetOptionsShift_Width
DMASetOptionsShift_Speed * 6
DMASetOptionsMask_Speed * 7 :SHL: DMASetOptionsShift_Speed
DMASetOptionsShift_PostDelay * 9
DMASetOptionsMask_PostDelay * 15 :SHL: DMASetOptionsShift_PostDelay
DMASetOptionsFlag_NoBursts * 1 :SHL: 13
DMASetOptionsFlag_NoClockSync * 1 :SHL: 14
DMASetTransferFlag_Stop * 1 :SHL: 0 ; raise TC after this transfer
DMAStatusFlag_NoUnstarted * 1 :SHL: 0 ; there are no transfers programmed but not yet started
DMAStatusFlag_Overrun * 1 :SHL: 1 ; this channel has not yet been used, or is over/underrunning
DMAStatusFlag_EarlyOverrun * 1 :SHL: 2 ; this channel over/underran during the last interrupt routine
]
OPT OldOpt
END
; Copyright 2001 Pace Micro Technology plc
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
; CallHAL
;
; On entry:
; r0-r3 hold first 4 arguments
; up to 4 more arguments are on the stack
;
; On exit:
; r4-r13 are always preserved
; optionally r0-r3 and r14 may be preserved
;
; Macro parameters:
; $routine = name of routine to call
; $savelist = list of additional registers to save
; across the call (from the set r0,r1,r2,r3,r14);
; note that if there is more than one register in the list,
; this means that the list must be enclosed by quotes
; $stackedargs = number of arguments that are on the stack (0-4)
MACRO
$label CallHAL $routine, $savelist, $stackedargs
LCLS reglist
reglist SETS "r12"
[ "$savelist"<>""
reglist SETS "$reglist,$savelist"
]
Push "$reglist"
MOV r14,pc
LDR pc,[r0,#HALDevice_$routine]
Pull "$reglist"
MEND
END
; Copyright 2002 Tematic Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
; > Sources.Command
ASSERT international
DMAChannels_Code
LDR r12, [r12]
Entry "r7-r11"
LDR r11, CtrlrList
TEQ r11, #0
EXIT EQ
; Cache information about the logical channel table.
ADR r1, I06
MOV r2, #0
BL MsgTrans_Lookup
STRVC r0, Header+4*0
ADDVC r1, r0, #1
01 LDRVCB r2, [r0], #1
TEQ r2, #0
BNE %BT01
SUBVC r1, r0, r1
STRVCB r1, Width+1*0
ADRVC r1, I07
MOVVC r2, #0
BLVC MsgTrans_Lookup
STRVC r0, Header+4*1
ADDVC r1, r0