Skip to content

GitLab

Commit a3e3822c authored by Tim Roddis's avatar Tim Roddis
Browse files

DMA changes for Phoebe (mostly remapping of channels).

parent a6c94776
Hide whitespace changes
Inline Side-by-side
Showing with 68 additions and 21 deletions
Version
View file @ a3e3822c
......@@ -13,13 +13,14 @@
; just as it was being suspended could end up blocking a channel.
; 04-Mar-94 0.06 SMC Fixed bugs in claim/release of sound DMA channels.
; 31-Oct-94 0.08 SMC CHANGE HISTORY TERMINATED, LOOK AT SRCFILER LOG FILE.
; 14-Aug-98 0.13 TGR Since we use CVS now: adaptations for Phoebe
GBLA Version
GBLS VString
GBLS Date
Version SETA 012 ; 000
VString SETS "0.12" ; "0.00"
Date SETS "24 Jul 1996" ; "13 Jul 1993"
Version SETA 013 ; 000
VString SETS "0.13" ; "0.00"
Date SETS "14 Aug 1996" ; "13 Jul 1993"
END
s/DMA
View file @ a3e3822c
......@@ -475,10 +475,12 @@ DMAForceActivate
MOV r11, #IOMD_Base ; Restore r11=IOMD base address.
LDR r2, [r8, #lcb_Physical] ; r2=physical channel number
CMP r2, #4 ; If it's not one of the general IO channels then
CMP r2, #NoIOChannels ; If it's not one of the general IO channels then
BCS %FT20 ; no need to program DMATCR.
MOV r1, #&03 ; Set cycle speed in DMATCR.
CMP r2, #4 ; channels 0..3 -> 0..3
ADDHS r2, r2, #4 ; 4..7 -> 8..b
MOV r1, r1, LSL r2
AND r3, r3, #lcbf_DMASpeed
MOV r3, r3, LSR #5
......@@ -503,6 +505,8 @@ DMAForceActivate
TST r1, #dmarf_Halted ; If transfer is halted then
EXITS NE ; wait for Service_PagesSafe to start it.
LDR r2, [r8, #lcb_Physical]
CMP r2, #4 ; channels 0..3 -> 0..3
ADDHS r2, r2, #4 ; 4..7 -> 8..b
30
IRQOff lr
MOV r3, #1 ; Enable interrupt for this channel.
......@@ -575,6 +579,9 @@ DMATerminate
LDR r1, [r8, #lcb_Physical] ; Otherwise, disable channel IRQ.
MOV r2, #1
LDRB lr, [r11, #IOMD_DMAMSK]
CMP r1, #4 ;
MOVHS lr, lr, LSL #4 ; shift it up (channels not contiguous)
BIC lr, lr, r2, LSL r1
STRB lr, [r11, #IOMD_DMAMSK]
......@@ -1426,6 +1433,7 @@ testloop
ANDEQ r2, r2, #dmar_PhysBits
MOVEQ r3, #1
LDREQB r4, [r11, #IOMD_DMASTA]
!!! WON'T WORK
BICEQ r4, r4, r3, LSL r2
STREQB r4, [r11, #IOMD_DMASTA]
]
......@@ -1482,6 +1490,8 @@ finished
|
LDRB lr, [r11, #IOMD_DMAMSK]
]
CMP r2, #4
MOVHS r1, r1, LSL #4
BIC lr, lr, r1, LSL r2
[ debugint
STR lr, [sp]
......@@ -1672,7 +1682,10 @@ halt
]
LDR r2, [r10, #dmar_Tag]
AND r2, r2, #dmar_PhysBits
MOV r3, #1
CMP r2, #4
MOVLO r3, #1
MOVHS r3, #1 :SHL: 4
BIC lr, lr, r3, LSL r2
[ debugint
STR lr, [sp, #12]
......
s/Front
View file @ a3e3822c
......@@ -18,8 +18,11 @@
; Structures and declarations.
;
NoLogicalChannels * 7
NoPhysicalChannels * 6
NoLogicalChannels * 11
NoPhysicalChannels * 11 ; incl. sound & PCI
NoIOChannels * 8 ; no. of standard I/O DMA channels
VIDC_Sound_DMA_In * 8
; Logical channel block.
^ 0
......
s/GetAll
View file @ a3e3822c
......@@ -71,6 +71,8 @@ international SETL true
GBLL IOMD
IOMD SETL true ; Assemble for real IOMD.
ASSERT IOMD
GBLL MemManager
MemManager SETL true ; Assemble memory management stuff.
......
s/Macros
View file @ a3e3822c
......@@ -117,7 +117,9 @@ $label ADR$cc $reg, IOMDArea
MACRO
$label DMARegBlk $blk, $phs
$label ADD $blk, r11, #IOMD_IO0CURA ; Base of DMA register blocks.
$label CMP $phs, #4
ADDLO $blk, r11, #IOMD_IO0CURA ; Base of DMA register blocks.
ADDHS $blk, r11, #IOMD2_IO4CURA - (4 :SHL: 5)
ADD $blk, $blk, $phs, LSL #5 ; Base + phys * 32
MEND
......
s/SWI
View file @ a3e3822c
......@@ -47,11 +47,18 @@ LogicalChannel
; DCD &070 ; Podule 7, DMA line 0, not supported
; DCD &071 ; Podule 7, DMA line 1, not supported
; DCD &100 ; On-board SCSI, not supported
DCD &101 ; On-board Floppy, channel 1
DCD &102 ; Parallel, channel 1
DCD &103 ; Sound out, channel 4
DCD &104 ; Sound in, channel 5
DCD &105 ; Network Card, channel 0
DCD &101 ; On-board Floppy, channel 0
DCD &102 ; Parallel, channel 5
DCD &103 ; Sound out, channel 8
; DCD &104 ; Sound in, not supported
; DCD &105 ; Network Card, not supported
DCD &106 ; IDE channel A, channel 7
DCD &107 ; IDE channel B, channel 6
DCD &108 ; Audio codec line 0, channel 1
DCD &109 ; Audio codec line 1, channel 4
DCD &10a ; PCI
DCD &10b ; channels
; put PCI stuff in here and give it dummy physical channels below 9, 10 etc.
ASSERT .-LogicalChannel = NoLogicalChannels :SHL: 2
......@@ -59,15 +66,32 @@ LogicalChannel
; PhysicalChannel table.
; Maps logical channel to physical channel.
;
GBLL PhoebeProto
PhoebeProto SETL {FALSE}
PhysicalChannel
[ :LNOT: PhoebeProto
DCB 2
DCB 3
|
DCB 2
DCB 1
]
DCB 0
DCB 5
DCB 8 ; fictional
DCB 7
DCB 6
[ :LNOT: PhoebeProto
DCB 1
DCB 4
DCB 5
|
DCB 3
DCB 4
]
DCB 9
DCB 10
ASSERT .-PhysicalChannel = NoPhysicalChannels
DCB 0
ALIGN
;---------------------------------------------------------------------------
......@@ -178,8 +202,10 @@ SWIRegisterChannel ROUT
Debug swi," channel handle =",r0
TEQ r7, #4 ; If not registering a sound channel then
TEQNE r7, #5
TEQ r7, #VIDC_Sound_DMA_In ; If not registering a sound channel then
; TEQNE r7, #5
EXIT NE ; exit.
Push "r0-r2"
......@@ -194,7 +220,7 @@ SWIRegisterChannel ROUT
STRB r6, [r8, #IOMD_IOTCR]
LDRB r6, [r8, #IOMD_DMAMSK] ; Disable sound channel and set up to claim device.
TEQ r7, #4
TEQ r7, #VIDC_Sound_DMA_In
MOVEQ r0, #IOMD_DMASound0_DevNo
ADREQL r1, DMAInterruptSound0
BICEQ r6, r6, #IOMD_DMA_SD0
......@@ -248,11 +274,11 @@ SWIDeregisterChannel
STR r7, [r8, #lcb_Flags]
BL DMAPurge ; r7=0 so new transfers can start.
TEQ r0, #4
TEQNE r0, #5
TEQ r0, #VIDC_Sound_DMA_In
; TEQNE r0, #5
EXIT NE ; If not a sound channel then exit.
TEQ r0, #4 ; Release appropriate sound device vector.
TEQ r0, #VIDC_Sound_DMA_In ; Release appropriate sound device vector.
MOVEQ r0, #IOMD_DMASound0_DevNo
ADREQL r1, DMAInterruptSound0
MOVNE r0, #IOMD_DMASound1_DevNo
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment