Commit cb964e6a authored by Kevin Bracey's avatar Kevin Bracey
Browse files

Cache on/off now manipulates I bit as well as C and B.

Needed for latest Kernels which allow independent control of the I bit,
rather than making it track C.

Version 0.19. Tagged as 'ARM-0_19'
parent 1987170f
......@@ -11,13 +11,13 @@
GBLS Module_HelpVersion
GBLS Module_ComponentName
GBLS Module_ComponentPath
Module_MajorVersion SETS "0.18"
Module_Version SETA 18
Module_MajorVersion SETS "0.19"
Module_Version SETA 19
Module_MinorVersion SETS ""
Module_Date SETS "03 Jun 2003"
Module_ApplicationDate SETS "03-Jun-03"
Module_Date SETS "06 May 2004"
Module_ApplicationDate SETS "06-May-04"
Module_ComponentName SETS "ARM"
Module_ComponentPath SETS "RiscOS/Sources/HWSupport/ARM"
Module_FullVersion SETS "0.18"
Module_HelpVersion SETS "0.18 (03 Jun 2003)"
Module_FullVersion SETS "0.19"
Module_HelpVersion SETS "0.19 (06 May 2004)"
END
/* (0.18)
/* (0.19)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.68.
*
*/
#define Module_MajorVersion_CMHG 0.18
#define Module_MajorVersion_CMHG 0.19
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 03 Jun 2003
#define Module_Date_CMHG 06 May 2004
#define Module_MajorVersion "0.18"
#define Module_Version 18
#define Module_MajorVersion "0.19"
#define Module_Version 19
#define Module_MinorVersion ""
#define Module_Date "03 Jun 2003"
#define Module_Date "06 May 2004"
#define Module_ApplicationDate "03-Jun-03"
#define Module_ApplicationDate "06-May-04"
#define Module_ComponentName "ARM"
#define Module_ComponentPath "RiscOS/Sources/HWSupport/ARM"
#define Module_FullVersion "0.18"
#define Module_HelpVersion "0.18 (03 Jun 2003)"
#define Module_LibraryVersionInfo "0:18"
#define Module_FullVersion "0.19"
#define Module_HelpVersion "0.19 (06 May 2004)"
#define Module_LibraryVersionInfo "0:19"
......@@ -32,9 +32,9 @@ Cache_Init
EXIT VS
TST r2, #CacheBit ; test configured cache bit
MOVEQ r1, #MMU_CacheOn_EORMask ; enable or disable the cache as appropriate.
MOVNE r1, #MMU_CacheOff_EORMask
MOV r2, #MMU_Cache_ANDMask
LDREQ r1, =MMU_CacheOn_EORMask ; enable or disable the cache as appropriate.
LDRNE r1, =MMU_CacheOff_EORMask
LDR r2, =MMU_Cache_ANDMask
MOV r0, #0 ; reason code for modifying control register
SWI XOS_MMUControl ; do it (NB SWI flushes cache itself if necessary)
EXIT
......@@ -109,9 +109,9 @@ Cache_Code ROUT
EXIT VS
TST r0, #CacheBit ; check if turning on or off
MOVEQ r1, #MMU_CacheOn_EORMask ; enable or disable the cache as appropriate.
MOVNE r1, #MMU_CacheOff_EORMask
MOV r2, #MMU_Cache_ANDMask
LDREQ r1, =MMU_CacheOn_EORMask ; enable or disable the cache as appropriate.
LDRNE r1, =MMU_CacheOff_EORMask
LDR r2, =MMU_Cache_ANDMask
MOV r0, #0 ; reason code for modifying control register
SWI XOS_MMUControl ; do it (NB SWI flushes cache itself if necessary)
EXIT
......
......@@ -32,8 +32,8 @@ f_messagesopen * 2_00000001
; MMU_CacheOn * MMUC_M + MMUC_C + MMUC_W + MMUC_P + MMUC_D + MMUC_L
; MMU_CacheOff * MMUC_M + MMUC_P + MMUC_D + MMUC_L
MMU_Cache_ANDMask * :NOT: (MMUC_C + MMUC_W)
MMU_CacheOn_EORMask * MMUC_C + MMUC_W
MMU_Cache_ANDMask * :NOT: (MMUC_I + MMUC_C + MMUC_W)
MMU_CacheOn_EORMask * MMUC_I + MMUC_C + MMUC_W
MMU_CacheOff_EORMask * 0
......
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