1. 05 Feb, 2020 3 commits
    • Robert Sprowson's avatar
      Don't overfill FIFO above 38400 baud · 856f51f5
      Robert Sprowson authored
      The default FCR transmit FIFO threshold was being used (=8) but HAL_UARTFIFOSize was declaring 64 (the maximum supported). For baud rates > 19200bps DualSerial always tries to use the transmit FIFO (switch 'NewTXStrategy' in the sources) so was happily pouring 64 bytes in and losing 56.
      
      UART.s: Enable enhanced functionality in EFR so that the FCR bits 4 & 5 can be written. Set them to 32, and declare that as the TX FIFO size to DualSerial.
      RegMap: Add EFR bit definitions.
      
      Version 0.13. Tagged as 'HAL_Titanium-0_13'
      856f51f5
    • Robert Sprowson's avatar
      Table entry rounding correction · ac7a080d
      Robert Sprowson authored
      Should add half the denominator, not twice. Resulted in table entries being approx 2us high.
      ac7a080d
    • Robert Sprowson's avatar
      Update HAL_PCIAddresses table · 3b69f552
      Robert Sprowson authored
      Converge on the 64b layout PCI address table (supported by PCI-0_18) to reduce variants in the wild.
      3b69f552
  2. 25 Aug, 2019 1 commit
    • Jeffrey Lee's avatar
      Fix stereo channels being reversed · 73237dbe
      Jeffrey Lee authored
      By default RISC OS/SoundDMA generates 32bit sample frames where
      the right channel is in the low 16 bits and the left channel is in
      the high 16 bits, as required by VIDC's 'wide' sound FIFO which
      stores a full 32bit frame per entry. This is in contrast to most
      newer systems RISC OS supports, with 'narrow' FIFOs which store
      only the data for a single channel per entry. Since I2S expects
      the left channel to be transmitted first, this generally means
      that RISC OS must switch to generating data such that the left
      channel is in the low 16 bits of each word (as supported via the
      audio HAL device 'StereoReverse' flag), or, as in this case, by
      instructing the hardware to swap the channels for us.
      
      Version 0.12. Tagged as 'HAL_Titanium-0_12'
      73237dbe
  3. 10 Feb, 2019 1 commit
    • Robert Sprowson's avatar
      Enable the PWM from TIMER14 · 2793a7a2
      Robert Sprowson authored
      At startup, output a 50/50 square wave on PL103. For boards without this connector it's a harmless unused ball.
      hdr/RegMap: Typo in PT_TOGGLE corrected
      hdr/StaticWS: Keep the logic base of registers
      CPUClk.s: Initial setup.
      Muxing.s: Configure pins.
      Top.s: Correction to address check to exclude OCMCRAM2 if loaded via JTAG.
      
      Version 0.11. Tagged as 'Titanium-0_11'
      2793a7a2
  4. 04 Dec, 2018 1 commit
    • Jeffrey Lee's avatar
      Improve SATA reliability when softloading · 62f5aff3
      Jeffrey Lee authored
      Detail:
        s/SATA - Perform a full reset of the SATA PLL during HAL startup, to fix the relock sequence sometimes leaving SATA nonfunctional
        hdr/RegMap - Add bit definitions for CTRL_CORE_SMA_SW_0 register
      Admin:
        Tested on Titanium
      
      
      Version 0.10. Tagged as 'Titanium-0_10'
      62f5aff3
  5. 11 Sep, 2018 1 commit
    • Robert Sprowson's avatar
      Tune up PHY and L3 clock divider · 4ce18e72
      Robert Sprowson authored
      Ensure the L3 bus clock post divide matches the DPLL_CORE H12 output. After investigation it seems the more recent mask ROM code changes this bit to its taste, so the bus was running at half speed, which caused occasional tearing when a large memory move happened in 2 head mode (eg. dragging a big window left/right).
      Update the SATA PHY pokes based on the latest TRM, this changes the clock-data-recovery settings, fixing an issue seen at high temperatures where the clock would need retraining excessively often.
      
      Version 0.09. Tagged as 'Titanium-0_09'
      4ce18e72
  6. 22 Jun, 2018 1 commit
    • Robert Sprowson's avatar
      Enable/disable DSPs at startup · c3b5f642
      Robert Sprowson authored
      The (unused) DSPs are in an undefined state at power on, reset them as described in i872 to make sure they're parked.
      Move the TypeB PLL setup later so the code before EarlyKernel fits into 1 flash sector when Debug={TRUE} again.
      
      Version 0.08. Tagged as 'Titanium-0_08'
      c3b5f642
  7. 05 Apr, 2018 1 commit
    • Robert Sprowson's avatar
      Have the DMM respect multiple MFLAG requests · c569ac04
      Robert Sprowson authored
      When several initiators set their MFLAGs, handle this gracefully by weighting the requests forwarded to the memory controller, rather than blocking one. The weight value is just the recommended one from the datasheet, the units seem arbitrary.
      Fixes a problem with large memory moves (eg. dragging a full size window in a 1920x1200x32bpp @ 60Hz mode) starving the video DMA because both waved their MFLAGs and one of the two lost.
      
      Version 0.07. Tagged as 'Titanium-0_07'
      c569ac04
  8. 29 Mar, 2018 1 commit
    • Robert Sprowson's avatar
      Add missing module to key scan dependencies · 8b64db9c
      Robert Sprowson authored
      In some circumstances XHCIDriver uses an RTSupport thread, but RTSupport was missed off the list of modules. Add it.
      Fixes problem with PixArt (093A/2510) OEM mouse getting stuck at power on (it stalls SetIdle transactions), but which worked if plugged in after power on when RTSupport is loaded.
      
      Version 0.06. Tagged as 'Titanium-0_06'
      8b64db9c
  9. 25 Jan, 2018 1 commit
  10. 12 Sep, 2017 1 commit
    • Robert Sprowson's avatar
      Turn off duplicate pullups · cfddc049
      Robert Sprowson authored
      There are discrete pullups (R719/R720) on IIC1, so the internal weak pullups are just wasting (80uA) electricity. Turn them off.
      
      Version 0.04. Tagged as 'Titanium-0_04'
      cfddc049
  11. 09 Sep, 2017 1 commit
    • ROOL's avatar
      Participate in keyboard scan dependencies · 28d8193f
      ROOL authored
      Detail:
        Add keyboard scan code with list of modules that the kernel needs to do the same.
        Reorder the HALEntries to match Kernel-5_89.
      Admin:
        Submission for USB bounty.
      
      Version 0.03. Tagged as 'Titanium-0_03'
      28d8193f
  12. 16 Oct, 2016 1 commit
  13. 06 Feb, 2016 1 commit
    • Robert Sprowson's avatar
      API enhancements and softload support · 25a4ecbd
      Robert Sprowson authored
      Added HAL_PlatformName implementation.
      Extend CPUClk API to 0.2 so the Portable module can get the core temperature.
      Add support for softloading by skipping the DRAM setup if already running from DRAM.
      
      Version 0.02. Tagged as 'Titanium-0_02'
      25a4ecbd
  14. 19 Dec, 2015 1 commit