Commit 34b996e6 authored by Jeffrey Lee's avatar Jeffrey Lee

Fix stereo channels being reversed

By default RISC OS/SoundDMA generates 32bit sample frames where
the right channel is in the low 16 bits and the left channel is in
the high 16 bits, as required by VIDC's 'wide' sound FIFO which
stores a full 32bit frame per entry. This is in contrast to most
newer systems RISC OS supports, with 'narrow' FIFOs which store
only the data for a single channel per entry. Since I2S expects
the left channel to be transmitted first, this generally means
that RISC OS must switch to generating data such that the left
channel is in the low 16 bits of each word (as supported via the
audio HAL device 'StereoReverse' flag), or, as in this case, by
instructing the hardware to swap the channels for us.
parent 2793a7a2
/* (0.11)
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
#define Module_MajorVersion_CMHG 0.11
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 10 Feb 2019
#define Module_MinorVersion_CMHG stereo_swap.1
#define Module_Date_CMHG 21 Aug 2019
#define Module_MajorVersion "0.11"
#define Module_Version 11
#define Module_MinorVersion ""
#define Module_Date "10 Feb 2019"
#define Module_MinorVersion "stereo_swap.1"
#define Module_Date "21 Aug 2019"
#define Module_ApplicationDate "10-Feb-19"
#define Module_ApplicationDate "21-Aug-19"
#define Module_ComponentName "Titanium"
#define Module_ComponentPath "cddl/RiscOS/Sources/HAL/Titanium"
#define Module_ComponentName "HAL_Titanium"
#define Module_FullVersion "0.11"
#define Module_HelpVersion "0.11 (10 Feb 2019)"
#define Module_FullVersion "0.11 (stereo_swap.1)"
#define Module_HelpVersion "0.11 (21 Aug 2019) stereo_swap.1"
#define Module_LibraryVersionInfo "0:11"
......@@ -405,7 +405,7 @@ AudioDevice_Activate ROUT
DCB 2_00010000 ; J=4
DCB 2_01000101 ; D=4444 (high half)
DCB 2_01110000 ; (low half)
DCB 2_10001010 ; AGC period, no dual rate mode, DAC data path enabled, L=L, R=R
DCB 2_10010100 ; AGC period, no dual rate mode, DAC data path enabled, L=R, R=L
DCB 2_10000000 ; BCLK output, WCLK input, no tristate, halt when PD, no 3D
DCB 2_00000001 ; 16b I2S, no resync, soft mute on resync
DCB 2_00000000 ; No data offset
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