Commit c3b5f642 authored by Robert Sprowson's avatar Robert Sprowson

Enable/disable DSPs at startup

The (unused) DSPs are in an undefined state at power on, reset them as described in i872 to make sure they're parked.
Move the TypeB PLL setup later so the code before EarlyKernel fits into 1 flash sector when Debug={TRUE} again.

Version 0.08. Tagged as 'Titanium-0_08'
parent c569ac04
/* (0.07)
/* (0.08)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.07
#define Module_MajorVersion_CMHG 0.08
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 05 Apr 2018
#define Module_Date_CMHG 22 Jun 2018
#define Module_MajorVersion "0.07"
#define Module_Version 7
#define Module_MajorVersion "0.08"
#define Module_Version 8
#define Module_MinorVersion ""
#define Module_Date "05 Apr 2018"
#define Module_Date "22 Jun 2018"
#define Module_ApplicationDate "05-Apr-18"
#define Module_ApplicationDate "22-Jun-18"
#define Module_ComponentName "Titanium"
#define Module_ComponentPath "cddl/RiscOS/Sources/HAL/Titanium"
#define Module_FullVersion "0.07"
#define Module_HelpVersion "0.07 (05 Apr 2018)"
#define Module_LibraryVersionInfo "0:7"
#define Module_FullVersion "0.08"
#define Module_HelpVersion "0.08 (22 Jun 2018)"
#define Module_LibraryVersionInfo "0:8"
......@@ -328,6 +328,24 @@ CM_MPU_MPU_CLKCTRL_CLKSEL_EMIF_DIV8 * 2:SHL:24
CM_MPU_MPU_MPU_DBG_CLKCTRL # 4
ASSERT @=&2C
;
; PRCM CM core AON DSP1
;
CMCoreAONDSP1_PhysBase * &4A005400
^ 0
CM_DSP1_CLKSTCTRL # 4
CM_DSP1_CLKSTCTRL_CLKACTIVITY_DSP1_GFCLK * 1:SHL:8
CM_DSP1_CLKSTCTRL_CLKTRCTRL_NO_SLEEP * 0:SHL:0
CM_DSP1_CLKSTCTRL_CLKTRCTRL_SW_SLEEP * 1:SHL:0
CM_DSP1_CLKSTCTRL_CLKTRCTRL_SW_WKUP * 2:SHL:0
CM_DSP1_CLKSTCTRL_CLKTRCTRL_HW_AUTO * 3:SHL:0
CM_DSP1_STATICDEP # 4
CM_DSP1_DYNAMICDEP # 4
# 5*4
CM_DSP1_DSP1_CLKCTRL # 4
ASSERT @=&24
;
; PRCM CM core IPU peripherals
;
......@@ -405,6 +423,24 @@ CM_IPU_I2C5_CLKCTRL # 4
CM_IPU_UART6_CLKCTRL # 4
ASSERT @=&84
;
; PRCM CM core AON DSP2
;
CMCoreAONDSP2_PhysBase * &4A005600
^ 0
CM_DSP2_CLKSTCTRL # 4
CM_DSP2_CLKSTCTRL_CLKACTIVITY_DSP2_GFCLK * 1:SHL:8
CM_DSP2_CLKSTCTRL_CLKTRCTRL_NO_SLEEP * 0:SHL:0
CM_DSP2_CLKSTCTRL_CLKTRCTRL_SW_SLEEP * 1:SHL:0
CM_DSP2_CLKSTCTRL_CLKTRCTRL_SW_WKUP * 2:SHL:0
CM_DSP2_CLKSTCTRL_CLKTRCTRL_HW_AUTO * 3:SHL:0
CM_DSP2_STATICDEP # 4
CM_DSP2_DYNAMICDEP # 4
# 5*4
CM_DSP2_DSP2_CLKCTRL # 4
ASSERT @=&24
;
; PRCM CM core DSS
;
......@@ -2483,6 +2519,69 @@ CM_CLKSEL_ABE_LP_CLK_CLK_DIV16 * 0:SHL:0
CM_CLKSEL_ABE_LP_CLK_CLK_DIV32 * 1:SHL:0
ASSERT @=&DC
;
; PRCM PRM DSP1
;
PRMDSP1_PhysBase * &4AE06400
^ 0
PM_DSP1_PWRSTCTRL # 4
PM_DSP1_PWRSTCTRL_POWERSTATE_SHIFT * 0
PM_DSP1_PWRSTCTRL_POWERSTATE_ON * 3:SHL:PM_DSP1_PWRSTCTRL_POWERSTATE_SHIFT
PM_DSP1_PWRSTCTRL_POWERSTATE_OFF * 0:SHL:PM_DSP1_PWRSTCTRL_POWERSTATE_SHIFT
PM_DSP1_PWRSTCTRL_POWERSTATE_INACTIVE * 2:SHL:PM_DSP1_PWRSTCTRL_POWERSTATE_SHIFT
PM_DSP1_PWRSTCTRL_POWERSTATE_MASK * 3:SHL:PM_DSP1_PWRSTCTRL_POWERSTATE_SHIFT
PM_DSP1_PWRSTCTRL_LOWPOWERSTATECHANGE * 1:SHL:4
PM_DSP1_PWRSTCTRL_DSP1_L1_ONSTATE_SHIFT * 16
PM_DSP1_PWRSTCTRL_DSP1_L1_ONSTATE_MASK * 3:SHL:PM_DSP1_PWRSTCTRL_DSP1_L1_ONSTATE_SHIFT
PM_DSP1_PWRSTCTRL_DSP1_L2_ONSTATE_SHIFT * 18
PM_DSP1_PWRSTCTRL_DSP1_L2_ONSTATE_MASK * 3:SHL:PM_DSP1_PWRSTCTRL_DSP1_L2_ONSTATE_SHIFT
PM_DSP1_PWRSTCTRL_DSP1_EDMA_ONSTATE_SHIFT * 20
PM_DSP1_PWRSTCTRL_DSP1_EDMA_ONSTATE_MASK * 3:SHL:PM_DSP1_PWRSTCTRL_DSP1_EDMA_ONSTATE_SHIFT
PM_DSP1_PWRSTST # 4
PM_DSP1_PWRSTST_POWERSTATEST_SHIFT * 0
PM_DSP1_PWRSTST_POWERSTATEST_MASK * 3:SHL:PM_DSP1_PWRSTST_POWERSTATEST_SHIFT
PM_DSP1_PWRSTST_POWERSTATEST_OFF * 0:SHL:PM_DSP1_PWRSTST_POWERSTATEST_SHIFT
PM_DSP1_PWRSTST_POWERSTATEST_RETENTION * 1:SHL:PM_DSP1_PWRSTST_POWERSTATEST_SHIFT
PM_DSP1_PWRSTST_POWERSTATEST_ON_INACTIVE * 2:SHL:PM_DSP1_PWRSTST_POWERSTATEST_SHIFT
PM_DSP1_PWRSTST_POWERSTATEST_ON_ACTIVE * 3:SHL:PM_DSP1_PWRSTST_POWERSTATEST_SHIFT
PM_DSP1_PWRSTST_LOGICSTATEST * 1:SHL:2
PM_DSP1_PWRSTST_DSP1_L1_STATEST_SHIFT * 4
PM_DSP1_PWRSTST_DSP1_L1_STATEST_MASK * 3:SHL:PM_DSP1_PWRSTST_DSP1_L1_STATEST_SHIFT
PM_DSP1_PWRSTST_DSP1_L1_STATEST_OFF * 0:SHL:PM_DSP1_PWRSTST_DSP1_L1_STATEST_SHIFT
PM_DSP1_PWRSTST_DSP1_L1_STATEST_ON * 3:SHL:PM_DSP1_PWRSTST_DSP1_L1_STATEST_SHIFT
PM_DSP1_PWRSTST_DSP1_L2_STATEST_SHIFT * 6
PM_DSP1_PWRSTST_DSP1_L2_STATEST_MASK * 3:SHL:PM_DSP1_PWRSTST_DSP1_L2_STATEST_SHIFT
PM_DSP1_PWRSTST_DSP1_L2_STATEST_OFF * 0:SHL:PM_DSP1_PWRSTST_DSP1_L2_STATEST_SHIFT
PM_DSP1_PWRSTST_DSP1_L2_STATEST_ON * 3:SHL:PM_DSP1_PWRSTST_DSP1_L2_STATEST_SHIFT
PM_DSP1_PWRSTST_DSP1_EDMA_STATEST_SHIFT * 8
PM_DSP1_PWRSTST_DSP1_EDMA_STATEST_MASK * 3:SHL:PM_DSP1_PWRSTST_DSP1_EDMA_STATEST_SHIFT
PM_DSP1_PWRSTST_DSP1_EDMA_STATEST_OFF * 0:SHL:PM_DSP1_PWRSTST_DSP1_EDMA_STATEST_SHIFT
PM_DSP1_PWRSTST_DSP1_EDMA_STATEST_ON * 3:SHL:PM_DSP1_PWRSTST_DSP1_EDMA_STATEST_SHIFT
PM_DSP1_PWRSTST_INTRANSITION * 1:SHL:20
PM_DSP1_PWRSTST_LASTPOWERSTATEENTERED_SHIFT * 24
PM_DSP1_PWRSTST_LASTPOWERSTATEENTERED_MASK * 3:SHL:PM_DSP1_PWRSTST_LASTPOWERSTATEENTERED_SHIFT
PM_DSP1_PWRSTST_LASTPOWERSTATEENTERED_OFF * 0:SHL:PM_DSP1_PWRSTST_LASTPOWERSTATEENTERED_SHIFT
PM_DSP1_PWRSTST_LASTPOWERSTATEENTERED_RETENTION * 1:SHL:PM_DSP1_PWRSTST_LASTPOWERSTATEENTERED_SHIFT
PM_DSP1_PWRSTST_LASTPOWERSTATEENTERED_ON_INACTIVE * 2:SHL:PM_DSP1_PWRSTST_LASTPOWERSTATEENTERED_SHIFT
PM_DSP1_PWRSTST_LASTPOWERSTATEENTERED_ON_ACTIVE * 3:SHL:PM_DSP1_PWRSTST_LASTPOWERSTATEENTERED_SHIFT
# 2*4
RM_DSP1_RSTCTRL # 4
RM_DSP1_RSTCTRL_RST_DSP1 * 1:SHL:1
RM_DSP1_RSTCTRL_RST_DSP1_LRST * 1:SHL:0
RM_DSP1_RSTST # 4
RM_DSP1_RSTST_RST_DSP1_LRST * 1:SHL:0
RM_DSP1_RSTST_RST_DSP1 * 1:SHL:1
RM_DSP1_RSTST_RST_DSP1_EMU * 1:SHL:2
RM_DSP1_RSTST_RST_DSP1_EMU_REQ * 1:SHL:3
# 3*4
RM_DSP1_DSP1_CONTEXT # 4
RM_DSP1_DSP1_CONTEXT_LOSTCONTEXT_DFF * 1:SHL:0
RM_DSP1_DSP1_CONTEXT_LOSTMEM_DSP_L1 * 1:SHL:8
RM_DSP1_DSP1_CONTEXT_LOSTMEM_DSP_L2 * 1:SHL:9
RM_DSP1_DSP1_CONTEXT_LOSTMEM_DSP_EDMA * 1:SHL:10
ASSERT @=&28
;
; PRCM PRM L3INIT
;
......@@ -2560,6 +2659,69 @@ CM_WKUPAON_UART10_CLKCTRL # 4
CM_WKUPAON_DCAN1_CLKCTRL # 4
ASSERT @=&8C
;
; PRCM PRM DSP2
;
PRMDSP2_PhysBase * &4AE07B00
^ 0
PM_DSP2_PWRSTCTRL # 4
PM_DSP2_PWRSTCTRL_POWERSTATE_SHIFT * 0
PM_DSP2_PWRSTCTRL_POWERSTATE_ON * 3:SHL:PM_DSP2_PWRSTCTRL_POWERSTATE_SHIFT
PM_DSP2_PWRSTCTRL_POWERSTATE_OFF * 0:SHL:PM_DSP2_PWRSTCTRL_POWERSTATE_SHIFT
PM_DSP2_PWRSTCTRL_POWERSTATE_INACTIVE * 2:SHL:PM_DSP2_PWRSTCTRL_POWERSTATE_SHIFT
PM_DSP2_PWRSTCTRL_POWERSTATE_MASK * 3:SHL:PM_DSP2_PWRSTCTRL_POWERSTATE_SHIFT
PM_DSP2_PWRSTCTRL_LOWPOWERSTATECHANGE * 1:SHL:4
PM_DSP2_PWRSTCTRL_DSP2_L1_ONSTATE_SHIFT * 16
PM_DSP2_PWRSTCTRL_DSP2_L1_ONSTATE_MASK * 3:SHL:PM_DSP2_PWRSTCTRL_DSP2_L1_ONSTATE_SHIFT
PM_DSP2_PWRSTCTRL_DSP2_L2_ONSTATE_SHIFT * 18
PM_DSP2_PWRSTCTRL_DSP2_L2_ONSTATE_MASK * 3:SHL:PM_DSP2_PWRSTCTRL_DSP2_L2_ONSTATE_SHIFT
PM_DSP2_PWRSTCTRL_DSP2_EDMA_ONSTATE_SHIFT * 20
PM_DSP2_PWRSTCTRL_DSP2_EDMA_ONSTATE_MASK * 3:SHL:PM_DSP2_PWRSTCTRL_DSP2_EDMA_ONSTATE_SHIFT
PM_DSP2_PWRSTST # 4
PM_DSP2_PWRSTST_POWERSTATEST_SHIFT * 0
PM_DSP2_PWRSTST_POWERSTATEST_MASK * 3:SHL:PM_DSP2_PWRSTST_POWERSTATEST_SHIFT
PM_DSP2_PWRSTST_POWERSTATEST_OFF * 0:SHL:PM_DSP2_PWRSTST_POWERSTATEST_SHIFT
PM_DSP2_PWRSTST_POWERSTATEST_RETENTION * 1:SHL:PM_DSP2_PWRSTST_POWERSTATEST_SHIFT
PM_DSP2_PWRSTST_POWERSTATEST_ON_INACTIVE * 2:SHL:PM_DSP2_PWRSTST_POWERSTATEST_SHIFT
PM_DSP2_PWRSTST_POWERSTATEST_ON_ACTIVE * 3:SHL:PM_DSP2_PWRSTST_POWERSTATEST_SHIFT
PM_DSP2_PWRSTST_LOGICSTATEST * 1:SHL:2
PM_DSP2_PWRSTST_DSP2_L1_STATEST_SHIFT * 4
PM_DSP2_PWRSTST_DSP2_L1_STATEST_MASK * 3:SHL:PM_DSP2_PWRSTST_DSP2_L1_STATEST_SHIFT
PM_DSP2_PWRSTST_DSP2_L1_STATEST_OFF * 0:SHL:PM_DSP2_PWRSTST_DSP2_L1_STATEST_SHIFT
PM_DSP2_PWRSTST_DSP2_L1_STATEST_ON * 3:SHL:PM_DSP2_PWRSTST_DSP2_L1_STATEST_SHIFT
PM_DSP2_PWRSTST_DSP2_L2_STATEST_SHIFT * 6
PM_DSP2_PWRSTST_DSP2_L2_STATEST_MASK * 3:SHL:PM_DSP2_PWRSTST_DSP2_L2_STATEST_SHIFT
PM_DSP2_PWRSTST_DSP2_L2_STATEST_OFF * 0:SHL:PM_DSP2_PWRSTST_DSP2_L2_STATEST_SHIFT
PM_DSP2_PWRSTST_DSP2_L2_STATEST_ON * 3:SHL:PM_DSP2_PWRSTST_DSP2_L2_STATEST_SHIFT
PM_DSP2_PWRSTST_DSP2_EDMA_STATEST_SHIFT * 8
PM_DSP2_PWRSTST_DSP2_EDMA_STATEST_MASK * 3:SHL:PM_DSP2_PWRSTST_DSP2_EDMA_STATEST_SHIFT
PM_DSP2_PWRSTST_DSP2_EDMA_STATEST_OFF * 0:SHL:PM_DSP2_PWRSTST_DSP2_EDMA_STATEST_SHIFT
PM_DSP2_PWRSTST_DSP2_EDMA_STATEST_ON * 3:SHL:PM_DSP2_PWRSTST_DSP2_EDMA_STATEST_SHIFT
PM_DSP2_PWRSTST_INTRANSITION * 1:SHL:20
PM_DSP2_PWRSTST_LASTPOWERSTATEENTERED_SHIFT * 24
PM_DSP2_PWRSTST_LASTPOWERSTATEENTERED_MASK * 3:SHL:PM_DSP2_PWRSTST_LASTPOWERSTATEENTERED_SHIFT
PM_DSP2_PWRSTST_LASTPOWERSTATEENTERED_OFF * 0:SHL:PM_DSP2_PWRSTST_LASTPOWERSTATEENTERED_SHIFT
PM_DSP2_PWRSTST_LASTPOWERSTATEENTERED_RETENTION * 1:SHL:PM_DSP2_PWRSTST_LASTPOWERSTATEENTERED_SHIFT
PM_DSP2_PWRSTST_LASTPOWERSTATEENTERED_ON_INACTIVE * 2:SHL:PM_DSP2_PWRSTST_LASTPOWERSTATEENTERED_SHIFT
PM_DSP2_PWRSTST_LASTPOWERSTATEENTERED_ON_ACTIVE * 3:SHL:PM_DSP2_PWRSTST_LASTPOWERSTATEENTERED_SHIFT
# 2*4
RM_DSP2_RSTCTRL # 4
RM_DSP2_RSTCTRL_RST_DSP2 * 1:SHL:1
RM_DSP2_RSTCTRL_RST_DSP2_LRST * 1:SHL:0
RM_DSP2_RSTST # 4
RM_DSP2_RSTST_RST_DSP2_LRST * 1:SHL:0
RM_DSP2_RSTST_RST_DSP2 * 1:SHL:1
RM_DSP2_RSTST_RST_DSP2_EMU * 1:SHL:2
RM_DSP2_RSTST_RST_DSP2_EMU_REQ * 1:SHL:3
# 3*4
RM_DSP2_DSP2_CONTEXT # 4
RM_DSP2_DSP2_CONTEXT_LOSTCONTEXT_DFF * 1:SHL:0
RM_DSP2_DSP2_CONTEXT_LOSTMEM_DSP_L1 * 1:SHL:8
RM_DSP2_DSP2_CONTEXT_LOSTMEM_DSP_L2 * 1:SHL:9
RM_DSP2_DSP2_CONTEXT_LOSTMEM_DSP_EDMA * 1:SHL:10
ASSERT @=&28
;
; PRCM PRM device
;
......
......@@ -387,10 +387,6 @@ EarlySetup
LDR a2, =CMCoreAONCkgen_PhysBase + CM_BASE_DPLL_MPU
BL SetupDPLLTypeA
ADR a1, ClockParamsUSB
LDR a2, =CMCoreCkgen_PhysBase + CM_BASE_DPLL_USB
BL SetupDPLLTypeB
ADR a1, ClockParamsGMAC
LDR a2, =CMCoreAONCkgen_PhysBase + CM_BASE_DPLL_GMAC
BL SetupDPLLTypeA
......@@ -399,10 +395,6 @@ EarlySetup
LDR a2, =CMCoreAONCkgen_PhysBase + CM_BASE_DPLL_ABE
BL SetupDPLLTypeA
ADR a1, ClockParamsPCIe
LDR a2, =CMCoreCkgen_PhysBase + CM_BASE_DPLL_PCIE_REF
BL SetupDPLLTypeB
; Mind the dog
BL SetupWatchdog
......@@ -527,7 +519,7 @@ EarlySetup
Stage '5'
; Now jump to the full ROM image just copied into DRAM
ADR a1, EarlyKernel
ADRL a1, EarlyKernel
ADRL a2, GPHeader
SUB a1, a1, a2 ; How far from start
ADD pc, a1, v2 ; Same offset into new image
......@@ -882,6 +874,9 @@ SetupDPLLTypeA ROUT
BEQ %BT10
MOV pc, lr
LTORG
ASSERT (. - GPHeader) <= GPBootSize
; SetupDPLLTypeB
; => a1 = table of parameters
; a2 = register base
......@@ -933,13 +928,66 @@ SetupDPLLTypeB ROUT
BEQ %BT10
MOV pc, lr
LTORG
ASSERT (. - GPHeader) <= GPBootSize
; DSPEnableDisable
DSPEnableDisable ROUT
; Power cycle each DSP per errata i872 to define their MFLAG
MOV ip, #0
10
ADR a4, DSPCMBases
ADR a3, DSPPRMBases
LDR a4, [a4, ip, LSL #2]
LDR a3, [a3, ip, LSL #2]
; Force wakeup, enable DSP clock, deassert reset
MOV a1, #CM_DSP1_CLKSTCTRL_CLKTRCTRL_SW_WKUP
STR a1, [a4, #CM_DSP1_CLKSTCTRL]
MOV a1, #CM_CLKCTRL_MODULEMODE_AUTO
STR a1, [a4, #CM_DSP1_DSP1_CLKCTRL]
MOV a1, #RM_DSP1_RSTCTRL_RST_DSP1_LRST
STR a1, [a3, #RM_DSP1_RSTCTRL]
20
LDR a1, [a4, #CM_DSP1_DSP1_CLKCTRL]
TST a1, #CM_CLKCTRL_IDLEST_MASK
BEQ %BT20
; Then power down and clock off
MOV a1, #CM_DSP1_CLKSTCTRL_CLKTRCTRL_HW_AUTO
STR a1, [a4, #CM_DSP1_CLKSTCTRL]
LDR a1, [a3, #PM_DSP1_PWRSTCTRL]
BIC a1, a1, #PM_DSP1_PWRSTCTRL_POWERSTATE_MASK
ASSERT PM_DSP1_PWRSTCTRL_POWERSTATE_OFF = 0
STR a1, [a3, #PM_DSP1_PWRSTCTRL]
MOV a1, #CM_CLKCTRL_MODULEMODE_DISABLE
STR a1, [a4, #CM_DSP1_DSP1_CLKCTRL]
MOV a1, #RM_DSP1_RSTCTRL_RST_DSP1_LRST :OR: RM_DSP1_RSTCTRL_RST_DSP1
STR a1, [a3, #RM_DSP1_RSTCTRL]
ADD ip, ip, #1
TEQ ip, #DSPCount
BNE %BT10
MOV pc, lr
DSPCMBases
DCD CMCoreAONDSP1_PhysBase
DCD CMCoreAONDSP2_PhysBase
DSPPRMBases
DCD PRMDSP1_PhysBase
DCD PRMDSP2_PhysBase
DSPCount * (. - DSPPRMBases):SHR:2
EarlyKernel ROUT
; Say hello
DebugTX "TiTwentyTwo"
; Crank up the other PLLs
ADRL a1, ClockParamsUSB
LDR a2, =CMCoreCkgen_PhysBase + CM_BASE_DPLL_USB
BL SetupDPLLTypeB
ADRL a1, ClockParamsPCIe
LDR a2, =CMCoreCkgen_PhysBase + CM_BASE_DPLL_PCIE_REF
BL SetupDPLLTypeB
; Get address of table of Kernel entries
ADRL a1, GPHeader + OSROM_HALSize
LDR v8, [a1, #OSHdr_Entries]
......@@ -955,6 +1003,9 @@ EarlyKernel ROUT
BL SetupDMAMux
BL SetupPinMux
; Put the DSPs into an idle state
BL DSPEnableDisable
; Initial 4k stack must be in 1st registered block
LDR sp, =DRAM_PhysBase + &1000
MOV a1, #0
......
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