Commit 856f51f5 authored by Robert Sprowson's avatar Robert Sprowson Committed by ROOL

Don't overfill FIFO above 38400 baud

The default FCR transmit FIFO threshold was being used (=8) but HAL_UARTFIFOSize was declaring 64 (the maximum supported). For baud rates > 19200bps DualSerial always tries to use the transmit FIFO (switch 'NewTXStrategy' in the sources) so was happily pouring 64 bytes in and losing 56.

UART.s: Enable enhanced functionality in EFR so that the FCR bits 4 & 5 can be written. Set them to 32, and declare that as the TX FIFO size to DualSerial.
RegMap: Add EFR bit definitions.

Version 0.13. Tagged as 'HAL_Titanium-0_13'
parent ac7a080d
/* (0.12)
/* (0.13)
*
* This file is automatically maintained by srccommit, do not edit manually.
*
*/
#define Module_MajorVersion_CMHG 0.12
#define Module_MajorVersion_CMHG 0.13
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 25 Aug 2019
#define Module_Date_CMHG 05 Feb 2020
#define Module_MajorVersion "0.12"
#define Module_Version 12
#define Module_MajorVersion "0.13"
#define Module_Version 13
#define Module_MinorVersion ""
#define Module_Date "25 Aug 2019"
#define Module_Date "05 Feb 2020"
#define Module_ApplicationDate "25-Aug-19"
#define Module_ApplicationDate "05-Feb-20"
#define Module_ComponentName "HAL_Titanium"
#define Module_FullVersion "0.12"
#define Module_HelpVersion "0.12 (25 Aug 2019)"
#define Module_LibraryVersionInfo "0:12"
#define Module_FullVersion "0.13"
#define Module_HelpVersion "0.13 (05 Feb 2020)"
#define Module_LibraryVersionInfo "0:13"
......@@ -3170,7 +3170,7 @@ UART_FCR_TX_FIFO_CLEAR * 1:SHL:2
UART_FCR_DMA_MODE * 1:SHL:3
UART_FCR_TX_FIFO_TRIG_SHIFT * 4
UART_FCR_TX_FIFO_TRIG_MASK * 3:SHL:UART_FCR_TX_FIFO_TRIG_SHIFT
UART_FCR_TX_FIFO_TRIG_OPTS * &3C381008
UART_FCR_TX_FIFO_TRIG_OPTS * &38201008
UART_FCR_RX_FIFO_TRIG_SHIFT * 6
UART_FCR_RX_FIFO_TRIG_MASK * 3:SHL:UART_FCR_RX_FIFO_TRIG_SHIFT
UART_FCR_RX_FIFO_TRIG_OPTS * &3C381008
......@@ -3182,8 +3182,15 @@ UART_IIR_IT_TYPE_MASK * &1F:SHL:UART_IIR_IT_TYPE_SHIFT
UART_IIR_FCR_MIRROR_SHIFT * 6
UART_IIR_FCR_MIRROR_MASK * 3:SHL:UART_IIR_FCR_MIRROR_SHIFT
UART_EFR # 0
UART_EFR_SW_FLOW_CONTROL_SHIFT * 0
UART_EFR_SW_FLOW_CONTROL_MASK * &F:SHL:UART_EFR_SW_FLOW_CONTROL_SHIFT
UART_EFR_ENHANCED_EN * 1:SHL:4
UART_EFR_SPECIAL_CHAR_DETECT * 1:SHL:5
UART_EFR_AUTO_RTS_EN * 1:SHL:6
UART_EFR_AUTO_CTS_EN * 1:SHL:7
UART_IIR_IRDA # 4
UART_LCR # 4
UART_LCR_CONFIG_MODE_B * &BF
UART_LCR_DIV_EN * 1:SHL:7
UART_LCR_BREAK_EN * 1:SHL:6
UART_LCR_PARITY_SHIFT * 3
......
......@@ -398,11 +398,22 @@ HAL_UARTStartUp ROUT
TST a3, #UART_SYSC_SOFTRESET
BNE %BT10
; Some sensible defaults
; Config mode 'B' to enable enhanced control bits
MOV a3, #UART_LCR_CONFIG_MODE_B
STRB a3, [ip, #UART_LCR]
LDRB a2, [ip, #UART_EFR]
ORR a2, a2, #UART_EFR_ENHANCED_EN
STRB a2, [ip, #UART_EFR]
MVN a3, a3
STRB a3, [ip, #UART_LCR] ; Out of mode 'B'
; Now the enhanced control bits are visible, set the transmit FIFO
MOV a3, #2_10:SHL:UART_FCR_TX_FIFO_TRIG_SHIFT
ADR a2, UARTSoftFCR
MOV a3, #0
STRB a3, [ip, #UART_FCR] ; Trigger at 32
STRB a3, [a2, a1] ; Soft FCR follows hardware
; Some sensible defaults
MOV a1, #UART_LCR_PARITY_NONE :OR: UART_LCR_NB_STOP1 :OR: \
UART_LCR_CHAR_LENGTH8
STRB a1, [ip, #UART_LCR] ; 8N1
......@@ -522,10 +533,11 @@ HAL_UARTModemStatus ROUT
HAL_UARTFIFOSize ROUT
CMP a1, #UARTCount
MOVCS a4, #0
MOVCC a4, #64 ; Both directions the same
MOVCC a4, #64 ; RX size
TEQ a2, #0
STRNE a4, [a2]
TEQ a3, #0
MOVNE a4, a4, LSR #1 ; TX size
STRNE a4, [a3]
MOV pc, lr
......
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