Commit 62f5aff3 authored by Jeffrey Lee's avatar Jeffrey Lee

Improve SATA reliability when softloading

Detail:
  s/SATA - Perform a full reset of the SATA PLL during HAL startup, to fix the relock sequence sometimes leaving SATA nonfunctional
  hdr/RegMap - Add bit definitions for CTRL_CORE_SMA_SW_0 register
Admin:
  Tested on Titanium


Version 0.10. Tagged as 'Titanium-0_10'
parent 4ce18e72
/* (0.09) /* (0.10)
* *
* This file is automatically maintained by srccommit, do not edit manually. * This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1. * Last processed by srccommit version: 1.1.
* *
*/ */
#define Module_MajorVersion_CMHG 0.09 #define Module_MajorVersion_CMHG 0.10
#define Module_MinorVersion_CMHG #define Module_MinorVersion_CMHG
#define Module_Date_CMHG 11 Sep 2018 #define Module_Date_CMHG 04 Dec 2018
#define Module_MajorVersion "0.09" #define Module_MajorVersion "0.10"
#define Module_Version 9 #define Module_Version 10
#define Module_MinorVersion "" #define Module_MinorVersion ""
#define Module_Date "11 Sep 2018" #define Module_Date "04 Dec 2018"
#define Module_ApplicationDate "11-Sep-18" #define Module_ApplicationDate "04-Dec-18"
#define Module_ComponentName "Titanium" #define Module_ComponentName "Titanium"
#define Module_ComponentPath "cddl/RiscOS/Sources/HAL/Titanium" #define Module_ComponentPath "cddl/RiscOS/Sources/HAL/Titanium"
#define Module_FullVersion "0.09" #define Module_FullVersion "0.10"
#define Module_HelpVersion "0.09 (11 Sep 2018)" #define Module_HelpVersion "0.10 (04 Dec 2018)"
#define Module_LibraryVersionInfo "0:9" #define Module_LibraryVersionInfo "0:10"
...@@ -1281,6 +1281,10 @@ CTRL_CORE_DTEMP_TEMP_SHIFT * 0 ...@@ -1281,6 +1281,10 @@ CTRL_CORE_DTEMP_TEMP_SHIFT * 0
CTRL_CORE_DTEMP_TEMP_BITS * 10 CTRL_CORE_DTEMP_TEMP_BITS * 10
CTRL_CORE_DTEMP_TEMP_MASK * &3FF:SHL:CTRL_CORE_DTEMP_TEMP_SHIFT CTRL_CORE_DTEMP_TEMP_MASK * &3FF:SHL:CTRL_CORE_DTEMP_TEMP_SHIFT
CTRL_CORE_SMA_SW_0 # 4 CTRL_CORE_SMA_SW_0 # 4
CTRL_CORE_SMA_SW_0_SATA_PLL_SOFT_RESET * 1:SHL:18
CTRL_CORE_SMA_SW_0_ISOLATE * 1:SHL:2
CTRL_CORE_SMA_SW_0_EMIF2_CKE_GATING_CTRL * 1:SHL:1
CTRL_CORE_SMA_SW_0_EMIF1_CKE_GATING_CTRL * 1:SHL:0
# 4 # 4
# 4 # 4
# 4 # 4
......
...@@ -69,6 +69,19 @@ SATAInit ROUT ...@@ -69,6 +69,19 @@ SATAInit ROUT
CallOS OS_MapInIO CallOS OS_MapInIO
STR a1, SATAPHY_LogBase STR a1, SATAPHY_LogBase
; SATA PHY power down sequence
LDR a3, ControlCore_LogBase
LDR a2, =((ClkOsc0 / 1000000) :SHL: CTRL_CORE_PHY_POWER_SATA_SATA_PWRCTRL_CLK_FREQ_SHIFT) :OR: \
CTRL_CORE_PHY_POWER_SATA_SATA_PWRCTRL_CLK_CMD_OFF
STR a2, [a3, #CTRL_CORE_PHY_POWER_SATA]
; Erratum i783: PLL requires a reset in order to re-lock
LDR a2, [a3, #CTRL_CORE_SMA_SW_0]
ORR a2, a2, #CTRL_CORE_SMA_SW_0_SATA_PLL_SOFT_RESET
STR a2, [a3, #CTRL_CORE_SMA_SW_0]
BIC a2, a2, #CTRL_CORE_SMA_SW_0_SATA_PLL_SOFT_RESET
STR a2, [a3, #CTRL_CORE_SMA_SW_0]
; Constant DPLL ratios for an output of 1500MHz ; Constant DPLL ratios for an output of 1500MHz
; REGN = 9, REGM = 750, SSC = off, PLL_SD = 6 ; REGN = 9, REGM = 750, SSC = off, PLL_SD = 6
MOV a2, #SATAPHY_PLL_CONFIGURATION2_PLL_IDLE MOV a2, #SATAPHY_PLL_CONFIGURATION2_PLL_IDLE
......
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