Commit 4ce18e72 authored by Robert Sprowson's avatar Robert Sprowson

Tune up PHY and L3 clock divider

Ensure the L3 bus clock post divide matches the DPLL_CORE H12 output. After investigation it seems the more recent mask ROM code changes this bit to its taste, so the bus was running at half speed, which caused occasional tearing when a large memory move happened in 2 head mode (eg. dragging a big window left/right).
Update the SATA PHY pokes based on the latest TRM, this changes the clock-data-recovery settings, fixing an issue seen at high temperatures where the clock would need retraining excessively often.

Version 0.09. Tagged as 'Titanium-0_09'
parent c3b5f642
/* (0.08)
/* (0.09)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.08
#define Module_MajorVersion_CMHG 0.09
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 22 Jun 2018
#define Module_Date_CMHG 11 Sep 2018
#define Module_MajorVersion "0.08"
#define Module_Version 8
#define Module_MajorVersion "0.09"
#define Module_Version 9
#define Module_MinorVersion ""
#define Module_Date "22 Jun 2018"
#define Module_Date "11 Sep 2018"
#define Module_ApplicationDate "22-Jun-18"
#define Module_ApplicationDate "11-Sep-18"
#define Module_ComponentName "Titanium"
#define Module_ComponentPath "cddl/RiscOS/Sources/HAL/Titanium"
#define Module_FullVersion "0.08"
#define Module_HelpVersion "0.08 (22 Jun 2018)"
#define Module_LibraryVersionInfo "0:8"
#define Module_FullVersion "0.09"
#define Module_HelpVersion "0.09 (11 Sep 2018)"
#define Module_LibraryVersionInfo "0:9"
......@@ -150,6 +150,8 @@ CMCoreAONCkgen_PhysBase * &4A005100
^ 0
CM_CLKSEL_CORE # 4
CM_CLKSEL_CORE_CLKSEL_L4 * 1:SHL:8
CM_CLKSEL_CORE_CLKSEL_L3 * 1:SHL:4
# 4
CM_CLKSEL_ABE # 4
# 4
......
......@@ -67,6 +67,12 @@ SetupClockMux ROUT
MOV a1, #CM_COREAON_L3INIT_60M_GFCLK_CLKCTRL_OPTFCLKEN_L3INIT_60M_GFCLK
STR a1, [a2, #CM_COREAON_L3INIT_60M_GFCLK_CLKCTRL]
; Ensure CORE_CLK = CORE_X2_CLK after post divide
LDR a2, =CMCoreAONCkgen_PhysBase
LDR a1, [a2, #CM_CLKSEL_CORE]
BIC a1, a1, #CM_CLKSEL_CORE_CLKSEL_L3
STR a1, [a2, #CM_CLKSEL_CORE]
; Turn on the shared OCP2SCP translators
LDR a2, =CMCoreL3INIT_PhysBase
MOV a1, #CM_CLKCTRL_MODULEMODE_AUTO
......
......@@ -103,7 +103,7 @@ SATAInit ROUT
; Tune up the PHY per Table 26-9 of TRM
LDR a2, =(2_01000:SHL:27) :OR: (2_0101:SHL:14) :OR: (2_00:SHL:5)
STR a2, [a1, #SATAPHYRX_ANA_PROGRAMMABILITY_REG1]
LDR a2, =(2_00:SHL:27) :OR: (2_0:SHL:26) :OR: (2_10:SHL:24) :OR: (2_0000001100110:SHL:11)
LDR a2, =(2_00001:SHL:19) :OR: (2_01100110:SHL:11)
STR a2, [a1, #SATAPHYRX_DIGITAL_MODES_REG1]
LDR a2, =(2_01:SHL:30)
STR a2, [a1, #SATAPHYRX_TRIM_REG4]
......
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