Tune up PHY and L3 clock divider
Ensure the L3 bus clock post divide matches the DPLL_CORE H12 output. After investigation it seems the more recent mask ROM code changes this bit to its taste, so the bus was running at half speed, which caused occasional tearing when a large memory move happened in 2 head mode (eg. dragging a big window left/right). Update the SATA PHY pokes based on the latest TRM, this changes the clock-data-recovery settings, fixing an issue seen at high temperatures where the clock would need retraining excessively often. Version 0.09. Tagged as 'Titanium-0_09'
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