Commit 4a30be7c authored by Robert Sprowson's avatar Robert Sprowson Committed by ROOL
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Inbound bus master fixes

Enable all transaction types in the root complex, and map inbound addresses 1:1 to match that declared by HAL_PCIAddresses. Otherwise attempting to bus master results in a 'target abort' being recorded in the status flags.

Tested with VL805 PCIe card - bytes were delivered where I expected them to be.

Version 0.14. Tagged as 'HAL_Titanium-0_14'
parent 856f51f5
/* (0.13) /* (0.14)
* *
* This file is automatically maintained by srccommit, do not edit manually. * This file is automatically maintained by srccommit, do not edit manually.
* *
*/ */
#define Module_MajorVersion_CMHG 0.13 #define Module_MajorVersion_CMHG 0.14
#define Module_MinorVersion_CMHG #define Module_MinorVersion_CMHG
#define Module_Date_CMHG 05 Feb 2020 #define Module_Date_CMHG 24 Jun 2020
#define Module_MajorVersion "0.13" #define Module_MajorVersion "0.14"
#define Module_Version 13 #define Module_Version 14
#define Module_MinorVersion "" #define Module_MinorVersion ""
#define Module_Date "05 Feb 2020" #define Module_Date "24 Jun 2020"
#define Module_ApplicationDate "05-Feb-20" #define Module_ApplicationDate "24-Jun-20"
#define Module_ComponentName "HAL_Titanium" #define Module_ComponentName "HAL_Titanium"
#define Module_FullVersion "0.13" #define Module_FullVersion "0.14"
#define Module_HelpVersion "0.13 (05 Feb 2020)" #define Module_HelpVersion "0.14 (24 Jun 2020)"
#define Module_LibraryVersionInfo "0:13" #define Module_LibraryVersionInfo "0:14"
...@@ -26,6 +26,7 @@ ...@@ -26,6 +26,7 @@
GET Hdr:ListOpts GET Hdr:ListOpts
GET Hdr:Macros GET Hdr:Macros
GET Hdr:System GET Hdr:System
GET Hdr:PCI
GET Hdr:OSEntries GET Hdr:OSEntries
GET hdr.RegMap GET hdr.RegMap
...@@ -470,6 +471,11 @@ PCIInit ROUT ...@@ -470,6 +471,11 @@ PCIInit ROUT
BICNE a3, a3, #PCIECTRL_TI_CONF_DEVICE_CMD_LTSSM_EN BICNE a3, a3, #PCIECTRL_TI_CONF_DEVICE_CMD_LTSSM_EN
STRNE a3, [a1, a2] STRNE a3, [a1, a2]
; Pass transaction types for each ATU window about to be opened
LDR a2, =PCICmd_IO :OR: PCICmd_Memory :OR: PCICmd_BusMaster :OR: \
PCICmd_ReportParityErrors :OR: PCICmd_ReportSystemErrors
STRH a2, [a1, #PCIConf_Command]
; We never read our own root complex configuration, lock in defaults ; We never read our own root complex configuration, lock in defaults
LDR a2, =:INDEX:PCIECTRL_PL_DBI_RO_WR_EN LDR a2, =:INDEX:PCIECTRL_PL_DBI_RO_WR_EN
LDR a3, [a1, a2] LDR a3, [a1, a2]
...@@ -498,7 +504,7 @@ PCIInit ROUT ...@@ -498,7 +504,7 @@ PCIInit ROUT
MOV a1, #PCIMemSpaceSize MOV a1, #PCIMemSpaceSize
LDR a2, =(2:SHL:OpenRegionShift) :OR: OpenIB :OR: (TypeM:SHL:OpenTypeShift) LDR a2, =(2:SHL:OpenRegionShift) :OR: OpenIB :OR: (TypeM:SHL:OpenTypeShift)
ORR a2, a2, v1, LSL #OpenCtrlShift ORR a2, a2, v1, LSL #OpenCtrlShift
ADR a3, PCIMemSpaces ADR a3, PCIMemIBTargetSpaces
ADR a4, PCIMemIBTargetSpaces ADR a4, PCIMemIBTargetSpaces
BL PCIOpenATU BL PCIOpenATU
......
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