Commit 3b69f552 authored by Robert Sprowson's avatar Robert Sprowson Committed by ROOL

Update HAL_PCIAddresses table

Converge on the 64b layout PCI address table (supported by PCI-0_18) to reduce variants in the wild.
parent 73237dbe
......@@ -678,8 +678,8 @@ HAL_PCIReadConfigWord
; <= a1 = bytes written to buffer
HAL_PCIAddresses ROUT
Push "v1, lr"
CMP a2, #7*4
MOVCS a3, #7*4
CMP a2, #10*4
MOVCS a3, #10*4
MOVCC a3, a2
MOV v1, a3 ; The smaller of the two
ADR a2, %FT10
......@@ -690,15 +690,15 @@ HAL_PCIAddresses ROUT
10
ASSERT PCIeL3Window1_PhysBase + PCIeL3Window_PhysSize = PCIeL3Window2_PhysBase
; Memory space offset, and range of addresses allocatable to it
DCD PCIeL3Window1_PhysBase + PCICfgSpaceSize
DCD PCIeL3Window1_PhysBase + PCICfgSpaceSize, &00000000
DCD &00000000
DCD (2 * PCIeL3Window_PhysSize) - PCICfgSpaceSize - PCIIOSpaceSize - 1
; IO space offset, and range of addresses allocatable to it
DCD PCIeL3Window2_PhysBase - PCIIOSpaceSize
DCD PCIeL3Window2_PhysBase - PCIIOSpaceSize, &00000000
DCD &00000000
DCD (2 * PCIIOSpaceSize) - 1
; Adjustment between SDRAM and PCI memory for inbound memory writes
DCD &00000000
DCD &00000000, &00000000
; HAL_PCISlotTable
; => a1 = buffer
......
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