Commit 2793a7a2 authored by Robert Sprowson's avatar Robert Sprowson

Enable the PWM from TIMER14

At startup, output a 50/50 square wave on PL103. For boards without this connector it's a harmless unused ball.
hdr/RegMap: Typo in PT_TOGGLE corrected
hdr/StaticWS: Keep the logic base of registers
CPUClk.s: Initial setup.
Muxing.s: Configure pins.
Top.s: Correction to address check to exclude OCMCRAM2 if loaded via JTAG.

Version 0.11. Tagged as 'Titanium-0_11'
parent 62f5aff3
/* (0.10)
/* (0.11)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.10
#define Module_MajorVersion_CMHG 0.11
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 04 Dec 2018
#define Module_Date_CMHG 10 Feb 2019
#define Module_MajorVersion "0.10"
#define Module_Version 10
#define Module_MajorVersion "0.11"
#define Module_Version 11
#define Module_MinorVersion ""
#define Module_Date "04 Dec 2018"
#define Module_Date "10 Feb 2019"
#define Module_ApplicationDate "04-Dec-18"
#define Module_ApplicationDate "10-Feb-19"
#define Module_ComponentName "Titanium"
#define Module_ComponentPath "cddl/RiscOS/Sources/HAL/Titanium"
#define Module_FullVersion "0.10"
#define Module_HelpVersion "0.10 (04 Dec 2018)"
#define Module_LibraryVersionInfo "0:10"
#define Module_FullVersion "0.11"
#define Module_HelpVersion "0.11 (10 Feb 2019)"
#define Module_LibraryVersionInfo "0:11"
......@@ -3096,7 +3096,7 @@ TIMER_TCLR_GPO_CFG * 1:SHL:14
TIMER_TCLR_CAPT_MODE_SINGLE * 0:SHL:13
TIMER_TCLR_CAPT_MODE_DOUBLE * 1:SHL:13
TIMER_TCLR_PT_PULSE * 0:SHL:12
TIMER_TCLR_PT_TOGGLE * 1:SHL:13
TIMER_TCLR_PT_TOGGLE * 1:SHL:12
TIMER_TCLR_TRG_NONE * 0:SHL:10
TIMER_TCLR_TRG_OVF * 1:SHL:10
TIMER_TCLR_TRG_OVF_MAT * 2:SHL:10
......
......@@ -181,6 +181,7 @@ SATAMAC_WRAPPER_LogBase # 4
USB3PHY_LogBase # 4
SDMA_LogBase # 4
MCASP3_LogBase # 4
PWM_LogBase # 4 ; Using TIMER14
L4_CFG_LogBase # 4 ; Base
CMCoreL4PER_LogBase # 4 ; Derived L4_CFG
......@@ -210,7 +211,7 @@ RTCDevice # 80
AudioDevice # 128
MixerDevice # 88
MixerSoftCopy # 6 * 8 ; Last set mix arguments
# 8
# 4
SATADevice # 64
CPUClkDevice # 96
# 8
......
......@@ -108,7 +108,40 @@ CPUSpeedCount SETA CPUSpeedCount + 1
; CPUClkInit
CPUClkInit ROUT
MOV pc, lr
Push "lr"
; Map in the PWM timer
MOV a1, #0
LDR a2, =TIMER14_PhysBase
MOV a3, #TIMER_PhysSize
CallOS OS_MapInIO
STR a1, PWM_LogBase
; Turn on the clock (source = TIMER_SYS_CLK = SYS_CLK1)
MOV a3, #CM_CLKCTRL_MODULEMODE_ENABLED
LDR ip, CMCoreL4PER_LogBase
LDR a2, =CM_L4PER3_TIMER14_CLKCTRL
STR a3, [ip, a2]
; Reset the PWM timer
MOV a3, #TIMER_TIOCP_CFG_SOFTRESET :OR: TIMER_TIOCP_CFG_IDLEMODE_SMART_IDLE
STR a3, [a1, #TIMER_TIOCP_CFG]
10
LDR a3, [a1, #TIMER_TIOCP_CFG]
TST a3, #TIMER_TIOCP_CFG_SOFTRESET
BNE %BT10
; Set at 50% duty, approx 38Hz
LDR a2, =&FFF80000 ; Sets frequency
STR a2, [a1, #TIMER_TLDR]
STR a2, [a1, #TIMER_TCRR]
LDR a2, =&FFFBBBB8 ; Sets duty
STR a2, [a1, #TIMER_TMAR]
LDR a2, =TIMER_TCLR_ST :OR: TIMER_TCLR_AR :OR: TIMER_TCLR_CE :OR: \
TIMER_TCLR_TRG_OVF_MAT :OR: TIMER_TCLR_PT_TOGGLE
STR a2, [a1, #TIMER_TCLR]
Pull "pc"
; CPUClkDeviceInit
CPUClkDeviceInit ROUT
......@@ -163,7 +196,7 @@ CPUClkDeviceInit ROUT
BL CPUClkAdjustPMIC
]
ADR a1, CPUClkDevice ; RAM copy needed for sb recovery
ADRL a1, CPUClkDevice ; RAM copy needed for sb recovery
ADR a2, CPUClkDeviceTemplate
MOV a3, #CPUClkDevice_Size
BL memcpy
......
......@@ -359,6 +359,10 @@ SetupPinMux ROUT
LDR a1, =CTRL_CORE_PAD_MUXMODE_E :OR: CTRL_CORE_PAD_PULLUDDISABLE
STR a1, [a2, #CTRL_CORE_PAD_MMC3_DAT1]
; PWM control FET
LDR a1, =CTRL_CORE_PAD_MUXMODE_7 :OR: CTRL_CORE_PAD_PULLUDDISABLE
STR a1, [a2, #CTRL_CORE_PAD_VIN1A_HSYNC0]
; The CMOS lock jumper
LDR a1, =CTRL_CORE_PAD_MUXMODE_E :OR: CTRL_CORE_PAD_INPUTENABLE :OR: \
CTRL_CORE_PAD_PULLUDDISABLE
......@@ -402,6 +406,7 @@ SetupPinMux ROUT
STR a1, [a2, #CTRL_CORE_PAD_MMC3_DAT0]
STR a1, [a2, #CTRL_CORE_PAD_MMC3_CMD]
STR a1, [a2, #CTRL_CORE_PAD_MMC3_CLK]
STR a1, [a2, #CTRL_CORE_PAD_MMC3_DAT4]
STR a1, [a2, #CTRL_CORE_PAD_MMC1_SDWP]
STR a1, [a2, #CTRL_CORE_PAD_USB2_DRVVBUS]
STR a1, [a2, #CTRL_CORE_PAD_USB1_DRVVBUS]
......
......@@ -1030,8 +1030,8 @@ EarlyKernel ROUT
LDR a2, =OCMCRAM2_PhysBase
ADD a3, a2, #OCMCRAM2_PhysSize
CMP a2, pc
CMPCS pc, a3
CMP pc, a2
CMPCS a3, pc
BHI %FT10 ; We're loaded via JTAG in that SRAM
MOV a4, #-1 ; All bits decoded
......
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