Commit 25a4ecbd authored by Robert Sprowson's avatar Robert Sprowson

API enhancements and softload support

Added HAL_PlatformName implementation.
Extend CPUClk API to 0.2 so the Portable module can get the core temperature.
Add support for softloading by skipping the DRAM setup if already running from DRAM.

Version 0.02. Tagged as 'Titanium-0_02'
parent 247795c6
/* (0.01)
/* (0.02)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.01
#define Module_MajorVersion_CMHG 0.02
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 19 Dec 2015
#define Module_Date_CMHG 06 Feb 2016
#define Module_MajorVersion "0.01"
#define Module_Version 1
#define Module_MajorVersion "0.02"
#define Module_Version 2
#define Module_MinorVersion ""
#define Module_Date "19 Dec 2015"
#define Module_Date "06 Feb 2016"
#define Module_ApplicationDate "19-Dec-15"
#define Module_ApplicationDate "06-Feb-16"
#define Module_ComponentName "Titanium"
#define Module_ComponentPath "cddl/RiscOS/Sources/HAL/Titanium"
#define Module_FullVersion "0.01"
#define Module_HelpVersion "0.01 (19 Dec 2015)"
#define Module_LibraryVersionInfo "0:01"
#define Module_FullVersion "0.02"
#define Module_HelpVersion "0.02 (06 Feb 2016)"
#define Module_LibraryVersionInfo "0:02"
......@@ -212,7 +212,7 @@ MixerDevice # 88
MixerSoftCopy # 6 * 8 ; Last set mix arguments
# 8
SATADevice # 64
CPUClkDevice # 88
CPUClkDevice # 96
# 8
OSEntryTable # 4 * (HighestOSEntry + 1)
SDMADMACDevice # 92 + (32 * 4) ; 1 controller + 32 pointers
......
......@@ -82,7 +82,7 @@ SOASize # 0
; Device struct
^ 0
# HALDevice_CPUClk_Size
# HALDevice_CPUClk_Size_0_2
CPUClk_SpeedIndexNow # 1
CPUClk_SpeedIndexNext # 1
# 2 ; Unused
......@@ -433,7 +433,7 @@ CPUClkDeviceTemplate
DCW HALDeviceType_SysPeri + HALDeviceSysPeri_CPUClk
DCW HALDeviceID_CPUClk_AM572x
DCD HALDeviceBus_Peri + HALDevicePeriBus_Sonics3220
DCD 0 ; API version 0
DCD 2 ; API version 0.2
DCD CPUClkDevice_Desc
DCD 0 ; Address - N/A
% 12 ; Reserved
......@@ -450,7 +450,9 @@ CPUClkDeviceTemplate
DCD CPUClk_Get
DCD CPUClk_Set
DCD CPUClk_Override
ASSERT (.-CPUClkDeviceTemplate) = HALDevice_CPUClk_Size
DCD CPUClk_GetOverride
DCD CPUClk_GetDieTemperature
ASSERT (.-CPUClkDeviceTemplate) = HALDevice_CPUClk_Size_0_2
DCB CPUDefaultIndex ; Current speed index
DCB -1 ; Next speed index
DCB 0, 0 ; Padding
......@@ -633,14 +635,30 @@ CPUClk_Set ROUT
Pull "sb, v1-v4, pc"
; CPUClk_Override
; CPUClk_[Get]Override
; => a1 = CPUClk device
; a2 = pointer to HAL specific override table
; a3 = number of entries in the override table
; a4 = format of override table
; <= a1 = success when 0, or -1 for failure
CPUClk_Override ROUT
MOV r0, #-1 ; Not supported
CPUClk_GetOverride ROUT
MOV a1, #-1 ; Not supported
MOV pc, lr
; CPUClk_GetDieTemperature
; => a1 = CPUClk device
; <= a1 = temperature in 0.1K steps
CPUClk_GetDieTemperature ROUT
Push "sb, lr"
SUB sb, a1, #:INDEX:CPUClkDevice
BL CPUClkDieTemp
MOV a2, #10
MOV a3, #2730
MLA a1, a1, a2, a3 ; Celcius to 10ths of kelvin
Pull "sb, pc"
END
......@@ -83,6 +83,7 @@
IMPORT HAL_SuperIOInfo
IMPORT HAL_ControllerAddress
IMPORT HAL_PlatformInfo
IMPORT HAL_PlatformName
IMPORT HAL_PCIReadConfigByte
IMPORT HAL_PCIReadConfigHalfword
IMPORT HAL_PCIReadConfigWord
......@@ -242,9 +243,9 @@ EntryTable
HALEntry HAL_PCISlotTable
HALEntry HAL_PCIAddresses
NullEntry ;HAL_ATAControllerInfo
NullEntry ;HAL_ATASetModes
NullEntry ;HAL_ATACableID
HALEntry HAL_PlatformName
NullEntry ;Unused
NullEntry ;Unused
HALEntry HAL_InitDevices
......
......@@ -83,7 +83,7 @@ HAL_Init ROUT
LDR a4, [a1, #OSHdr_Entries]
ADD a4, a4, a1 ; Src absolute
ADR a3, OSEntryTable ; Dst absolute
ADRL a3, OSEntryTable ; Dst absolute
10
SUBS a2, a2, #1
LDR ip, [a4, a2, LSL #2]
......
......@@ -42,6 +42,7 @@
EXPORT HAL_SuperIOInfo
EXPORT HAL_ControllerAddress
EXPORT HAL_PlatformInfo
EXPORT HAL_PlatformName
IMPORT HAL_CounterDelay
IMPORT memset
IMPORT PMICPowerOff
......@@ -315,4 +316,13 @@ HAL_PlatformInfo ROUT
STR a1, [a3]
MOV pc, lr
; HAL_PlatformName
; <= a1 = pointer to description
HAL_PlatformName ROUT
ADR a1, %FT10
MOV pc, lr
10
DCB "Titanium", 0
ALIGN
END
......@@ -69,6 +69,22 @@ ParamM3 # 2 ; Type A only parameters
ParamH1y # 2 * 4
ParamH2y # 2 * 4
^ 0
ParamConfig # 4 ; Memory parameter table layout
ParamConfig2 # 4
ParamByteWidth # 1
ParamRows # 1
ParamColumns # 1
ParamBanks # 1
ParamTiming1 # 4
ParamRefresh # 4
ParamTiming2 # 4
ParamTiming3 # 4
ParamTimingZQ # 4
ParamPhyControl # 4
ParamExtPhyRegs # 25 * 4
ParamEnd # 4
GPHeader
; Needed by the mask ROM loader
DCD GPBootSize
......@@ -448,13 +464,36 @@ EarlySetup
; Small stack in SRAM so we can at least try to follow ATPCS
LDR sp, =OCMCRAM1_PhysBase + GPBootSize + &1000
; Start the DRAM and present it to the DMM
; Set up QSPI even if not subsequently used
BL SetupQSPI
; If we're running from DRAM (softload) leave the DRAM setup alone
MOV a1, pc, LSR #GPBootSizeShift
LDR a2, =DRAM_PhysBase:SHR:GPBootSizeShift
ASSERT DRAM_PhysBase > OCMCRAM1_PhysBase
ASSERT DRAM_PhysBase > OCMCRAM2_PhysBase
CMP a1, a2
BCC %FT30
ADR a1, MemParamsEMIF1
BL ReportDRAM
MOV v1, a1
ADR a1, MemParamsEMIF2
BL ReportDRAM
ADD v1, v1, a1 ; Total DRAM amount (for later)
B EarlyKernel
30
Stage '2'
; Loaded from JTAG or QSPI, initialise the DRAM clock
ADR a1, ClockParamsDDR
LDR a2, =CMCoreAONCkgen_PhysBase + CM_BASE_DPLL_DDR
BL SetupDPLLTypeA
Stage '2'
Stage '3'
; Start the DRAM and present it to the DMM
! 0, "TODO! Detect vendor from pullup (when more than 1 vendor)"
ADR a1, MemParamsEMIF1
LDR a2, =EMIF1_PhysBase
......@@ -470,11 +509,9 @@ EarlySetup
BL SetupDMM
MOV v1, a1 ; Total DRAM amount (for later)
Stage '3'
Stage '4'
; Load the rest of the ROM image into DRAM
BL SetupQSPI
MOV a1, pc, LSR #GPBootSizeShift
LDR a2, =OCMCRAM1_PhysBase:SHR:GPBootSizeShift
TEQ a1, a2
......@@ -487,7 +524,7 @@ EarlySetup
BL MemCopyQSPI
MOV v2, a1
Stage '4'
Stage '5'
; Now jump to the full ROM image just copied into DRAM
ADR a1, EarlyKernel
......@@ -608,22 +645,6 @@ EarlyStageReport ROUT
; <= a1 = memory size in bytes on that controller
SetupDRAM ROUT
^ 0
ParamConfig # 4
ParamConfig2 # 4
ParamByteWidth # 1
ParamRows # 1
ParamColumns # 1
ParamBanks # 1
ParamTiming1 # 4
ParamRefresh # 4
ParamTiming2 # 4
ParamTiming3 # 4
ParamTimingZQ # 4
ParamPhyControl # 4
ParamExtPhyRegs # 25 * 4
ParamEnd # 4
; Ensure no override
LDR ip, =CMCoreAONCkgen_PhysBase
MOV a3, #0
......@@ -702,6 +723,9 @@ ParamEnd # 4
LDR a3, [a1, #ParamConfig]
STR a3, [a2, #EMIF_SDRAM_CONFIG]
; Fall through...
ReportDRAM ROUT
; Report the byte size
LDRB a4, [a1, #ParamByteWidth]
LDRB a3, [a1, #ParamRows]
......
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