1. 07 Jan, 2023 1 commit
    • Jeffrey Lee's avatar
      Fix timer 1 interrupts · 79df9569
      Jeffrey Lee authored
      HAL timer 1 interrupts were never being enabled, and use of an
      uninitialised register in HAL_TimerIRQClear meant it was potentially
      clearing both interrupts instead of just one of them.
      Version 0.49. Tagged as 'HAL_PineA64-0_49'
  2. 13 Jul, 2022 2 commits
    • Ben Avison's avatar
      Rework SD support · 38e10a8b
      Ben Avison authored
      * Much of the SMHC driver code is moved out to a separate library, SMHCLib,
        to facilitate code re-use with the RK3399 port.
      * Refactor most assembly parts of SD HAL device into C, adapting to support
        arbitrary controller parameters at runtime, rather than being hard-coded to
        controller 0.
      * Add power and pin configuration and discovery of controller 1 (for WiFi) and
        2 (for eMMC).
      * Redesign DMA algorithm to use relatively small, double-banked buffers of
        cached RAM. This reduces overall memory requirements from 16 MB to 528 K
        per controller (avoiding memory exhaustion in PCI Manager), allows the
        transfer length limit to be lifted to 32 MB (the maximum that can be
        generated by SDFS - DiscOps larger than that are split into 32 MB
        operations) and removes a speed bottleneck caused by the Cortex-A53's slow
        uncached memory accesses.
      * All errors from the state machine were getting overwritten with
        "Command aborted", thereby preventing nuanced responses to expected errors.
      * Correct size of HAL device workspace in hdr.StaticWS - was previously
        allocating 4 bytes too little for each controller, leading to overflow.
      * Implement card detect - now you can swap micro-SD cards at runtime.
      * Improve wait-for-controller state machine states: implement wait-for-CMD
        by polling FSM_STA, and change wait-for-DAT to use FSM_BUSY rather than
        CARD_BUSY (by analogy to the SDHCI state machine, these states are supposed
        to wait for the *controller* to be not-busy, rather than the *card*).
      * Redesign clock divider algorithm. The old code wasn't producing the
        advertised clock speeds. Enable 50 MHz clock speed, on the assumption that
        any problems encountered previously were the result of not actually setting
        the clock to 50 MHz.
      * Accommodate the differences in the lower card status bits that have arisen
        between recent SD and MMC standards.
      * read_IRQ_status() copied some handling of interrupt status bit interactions
        from SDIODriver's SDHCI code. I believe these were a result of cramming
        extra error conditions into a standard register set in a
        backward-compatible way, and shouldn't be applied to the A64's rather
        different controller.
      * Prioritise the controller error status bits in the same order as the SDHCI
        driver does, for consistent error generation.
      * Set response and data timeouts correctly. With this in place, response
        timeout interrupts are generated by the controller, and we no longer need
        the fudge to handle the lack of response to CMD5 (an SDIO-specific
        command) during the bus probe process.
      * Fix a confusion between `&&` and `&` which meant that whenever a command
        fails, the test for whether the controller reset has completed would
        always run until its timeout, which made bus scans far slower than
      * Enable command response CRC error checking when appropriate.
      * Don't enable data CRC errors for operations with no data transfer.
      * Do identification phase at 50 kHz to allow for weak pull-ups and lack of
        specific support for open-drain mode in the controller.
      * Avoid data aborts due to dereferencing uninitialised scatter list pointers
        in non-data commands.
      * Support special behaviour of (e)MMC CMD19 (no CRC status on a write) -
        without this, no (e)MMC device would complete initialisation.
      * Support background operations.
      * Support scatter transfers.
      * Honour card busy signalling after both responses and data transfers, and
        wait for auto-CMD12 completion where applicable; should avoid potential
        occurrences of data loss.
      * Remove misleading SDHCI HAL device initialisation in s.SDIO (later
        overwritten in c.device).
      * Initialise SDHCI HAL device entries in c.device in increasing address order.
      * Remove unused state machine states, functions, data structures, debug,
        source files, commented-out code etc.
      * Rework HAL SB register setup, and only do so when absolutely necessary (also
        fixes bug where get_capabilities() returned with SB corrupted).
      * Remove PIC attributes from assembly sources - plenty of examples of absolute
        addresses being stored in read-only areas!
      * Link with SyncLib rather than using a local copy.
      Version 0.48. Tagged as 'HAL_PineA64-0_48'
    • Ben Avison's avatar
      Add cross-compilation support · 7158c65e
      Ben Avison authored
      Switch to using shared "HAL" makefile fragment; otherwise mostly a case of
      changing included filespecs to be case-correct and OS-neutral.
  3. 09 Feb, 2022 1 commit
  4. 21 Jan, 2022 1 commit