Commit ff60f3e7 authored by Robert Sprowson's avatar Robert Sprowson
Browse files

Whitespace changes

Code and hashes lined up nicely.
Not tagged.
parent cf16b564
......@@ -37,85 +37,85 @@ SDHCISize * :INDEX:@
MaxSDControllers * 2 ; I don't think any platform uses all 3 controllers?
^ 0,sb
^ 0,sb
BoardConfig # BoardConfig_Size
; NOTE: Almost all code assumes the board config is at the start. You have been warned!
OSheader # 4
OSentries # 4*(HighestOSEntry+1)
L3_Log # 4 ; L3 base logical address
L4_Per_Log # 4 ; L4 Per base logical address
L4_ABE_Log # 4 ; L4 ABE base logical address
L4_Core_Log # 4 ; L4 Core/Wakeup base logical address
L4_Wakeup_Log # 4 ; L4 Wakeup base logical address
MPU_INTC_Log # 4 ; MPU_INTC logical address
Timers_Log # 4 ; Timers logical base address
L4_ClockMan_Log # 4 ; L4_ClockMan base address
L4_ClockMan2_Log # 4 ; L4_ClockMan2 base address
L4_PowerMan_Log # 4 ; L4_PowerMan base address
L4_32KTIMER_Log # 4 ; L4_32KTIMER base address
L4_USBTLL_Log # 4 ; L4_USBTLL base address
L4_USB_Host_Log # 4 ; L4_USB_Host base address
L4_USB_OTG_Log # 4 ; L4_USB_OTG base address
GPMC_Regs_Log # 4 ; GPMC_Regs base address
sys_clk # 4 ; System clock speed in Hz
Timer_DelayMul # 4 ; sys_clk/100KHz
HALInitialised # 4 ; Flag for whether HAL_Init is done yet
NVMemoryFound # 4 ; Size of EEPROM detected (may be 0)
L4_Display_Log # 4 ; L4_Display base address
L4_sDMA_Log # 4 ; L4_sDMA logical address
IntSRAM_Log # 4 ; SRAM logical address
L4_GPIO_Table # 0 ; Lookup table for GPIO addresses
L4_GPIO1_Log # 4 ; L4_GPIO1 base address
L4_GPIO2_Log # 4 ; L4_GPIO2 base address
L4_GPIO3_Log # 4 ; L4_GPIO3 base address
L4_GPIO4_Log # 4 ; L4_GPIO4 base address
L4_GPIO5_Log # 4 ; L4_GPIO5 base address
L4_GPIO6_Log # 4 ; L4_GPIO6 base address
OSheader # 4
OSentries # 4*(HighestOSEntry+1)
L3_Log # 4 ; L3 base logical address
L4_Per_Log # 4 ; L4 Per base logical address
L4_ABE_Log # 4 ; L4 ABE base logical address
L4_Core_Log # 4 ; L4 Core/Wakeup base logical address
L4_Wakeup_Log # 4 ; L4 Wakeup base logical address
MPU_INTC_Log # 4 ; MPU_INTC logical address
Timers_Log # 4 ; Timers logical base address
L4_ClockMan_Log # 4 ; L4_ClockMan base address
L4_ClockMan2_Log # 4 ; L4_ClockMan2 base address
L4_PowerMan_Log # 4 ; L4_PowerMan base address
L4_32KTIMER_Log # 4 ; L4_32KTIMER base address
L4_USBTLL_Log # 4 ; L4_USBTLL base address
L4_USB_Host_Log # 4 ; L4_USB_Host base address
L4_USB_OTG_Log # 4 ; L4_USB_OTG base address
GPMC_Regs_Log # 4 ; GPMC_Regs base address
sys_clk # 4 ; System clock speed in Hz
Timer_DelayMul # 4 ; sys_clk/100KHz
HALInitialised # 4 ; Flag for whether HAL_Init is done yet
NVMemoryFound # 4 ; Size of EEPROM detected (may be 0)
L4_Display_Log # 4 ; L4_Display base address
L4_sDMA_Log # 4 ; L4_sDMA logical address
IntSRAM_Log # 4 ; SRAM logical address
L4_GPIO_Table # 0 ; Lookup table for GPIO addresses
L4_GPIO1_Log # 4 ; L4_GPIO1 base address
L4_GPIO2_Log # 4 ; L4_GPIO2 base address
L4_GPIO3_Log # 4 ; L4_GPIO3 base address
L4_GPIO4_Log # 4 ; L4_GPIO4 base address
L4_GPIO5_Log # 4 ; L4_GPIO5 base address
L4_GPIO6_Log # 4 ; L4_GPIO6 base address
MaxI2CControllers * 4
I2C_Table # (MaxI2CControllers*I2CBlockSize) ; I2C HW ptrs & transfer states
[ DebugInterrupts
LastInterrupt_IRQ # 4 ; Last IRQ, -1 if cleared
LastInterrupt_FIQ # 4 ; Last FIQ, -1 if cleared
LastInterrupt_IRQ # 4 ; Last IRQ, -1 if cleared
LastInterrupt_FIQ # 4 ; Last FIQ, -1 if cleared
[ ExtraDebugInterrupts
ExtraDebugIRQEnabled # 4 ; Nonzero if extra debugging enabled
ExtraDebugIRQEnabled # 4 ; Nonzero if extra debugging enabled
]
]
UARTFCRSoftCopy # 4
NCNBWorkspace # 4 ; Base of ncnb workspace
NCNBAllocNext # 4 ; next free address in ncnb workspace
UARTFCRSoftCopy # 4
NCNBWorkspace # 4 ; Base of ncnb workspace
NCNBAllocNext # 4 ; next free address in ncnb workspace
DMAPktSz_Audio # 4 ; DMA packet size to use for audio transfers (McPDM DL)
DMAPktSz_Audio # 4 ; DMA packet size to use for audio transfers (McPDM DL)
USBHAL_WS # USBHAL_WS_Size ; USB workspace for keyboard scan
USBHAL_WS # USBHAL_WS_Size ; USB workspace for keyboard scan
SDMAWS # SDMA_WorkspaceSize
SDMAWS # SDMA_WorkspaceSize
VideoDevice # Video_DeviceSize
VideoBoardConfig # VideoBoardConfig_Size
VideoDevice # Video_DeviceSize
VideoBoardConfig # VideoBoardConfig_Size
AudioWS # Audio_WorkspaceSize
GPIOWS # HALDevice_GPIO_Size
NVRAMWS # HALDeviceSize
AudioWS # Audio_WorkspaceSize
GPIOWS # HALDevice_GPIO_Size
NVRAMWS # HALDeviceSize
SDIOWS # SDHCISize * MaxSDControllers
SDIOWS # SDHCISize * MaxSDControllers
; align on 16 byte boundary
# (((:INDEX:@)+15):AND::NOT:15)-(:INDEX:@)
# (((:INDEX:@)+15):AND::NOT:15)-(:INDEX:@)
USBAllocAreaSize * 16*1024
; With an ordinary setup, about half of this memory gets used.
; About 3K goes to some big allocs (looks like the bus structs)
USBAllocArea # USBAllocAreaSize
USBAllocArea # USBAllocAreaSize
HAL_WsSize * :INDEX:@
HAL_WsSize * :INDEX:@
] ; __HAL_STATICWS_HDR__
......
......@@ -763,75 +763,75 @@ read_bytes
HAL_VideoIICOp
; Make sure we've got a valid IIC bus to use
LDRB a4, [sb, #BoardConfig_VideoI2C]
CMP a4, #255
MOV ip, #0
STREQ ip, [a3]
MOVEQ a1, #IICStatus_Error
MOVEQ pc, lr
LDRB a4, [sb, #BoardConfig_VideoI2C]
CMP a4, #255
MOV ip, #0
STREQ ip, [a3]
MOVEQ a1, #IICStatus_Error
MOVEQ pc, lr
; Check for input passed end
UBFX a4, a1, #0, #16
CMP a4, #256
STRCS ip, [a3]
MOVCS a1, #IICStatus_Completed
MOVCS pc, lr
UBFX a4, a1, #0, #16
CMP a4, #256
STRCS ip, [a3]
MOVCS a1, #IICStatus_Completed
MOVCS pc, lr
; Clip request at end
Push "a1-a3,lr"
LDR a3, [a3]
ADD ip, a4, a3
CMP ip, #256
RSBHI a3, a4, #256
Push "a1-a3,lr"
LDR a3, [a3]
ADD ip, a4, a3
CMP ip, #256
RSBHI a3, a4, #256
; Build a set of iic_transfer blocks and call RISCOS_IICOpV
; We construct two iic_transfer blocks
; - First block is a single byte write containing the start address (lower 8 bits of r0)
; - Second block is a read. r2 bytes written to r1.
; Block 2:
UBFX a1, a1, #16, #8 ; Extract base IICAddress
Push "a1-a3" ; Push the block on the stack (a2 & a3 are already correct)
UBFX a1, a1, #16, #8 ; Extract base IICAddress
Push "a1-a3" ; Push the block on the stack (a2 & a3 are already correct)
; Block 1:
BIC a1, a1, #1 ; Clear RnW of base address
ADD a2, sp, #12 ; sp+12 should point to the 8 bit offset
MOV a3, #1
Push "a1-a3"
BIC a1, a1, #1 ; Clear RnW of base address
ADD a2, sp, #12 ; sp+12 should point to the 8 bit offset
MOV a3, #1
Push "a1-a3"
; Now attempt to start the transfer
LDRB a2, [sb, #BoardConfig_VideoI2C]
MOV a2, a2, LSL #24
ADD a2, a2, #2
MOV a1, sp
LDRB a2, [sb, #BoardConfig_VideoI2C]
MOV a2, a2, LSL #24
ADD a2, a2, #2
MOV a1, sp
; If HAL_Init isn't done yet, we can't use RISCOS_IICOpV
LDR a3, HALInitialised
CMP a3, #0
BEQ %FT10
LDR a3, OSentries+4*OS_IICOpV
BLX a3
LDR a3, HALInitialised
CMP a3, #0
BEQ %FT10
LDR a3, OSentries+4*OS_IICOpV
BLX a3
; Unmap RISC OS error numbers to IICStatus return codes
ASSERT IICStatus_Completed = 0
TEQ a1, #0
LDRNE a1, [a1]
LDRNE lr, =ErrorNumber_IIC_NoAcknowledge
SUBNE a1, a1, lr ; 0/1/2 = NoAck/Error/Busy
USATNE a1, #2, a1 ; 4+ => 3 = Error
ADRNE lr, %FT05
LDRNEB a1, [lr, a1]
B %FT20
ASSERT IICStatus_Completed = 0
TEQ a1, #0
LDRNE a1, [a1]
LDRNE lr, =ErrorNumber_IIC_NoAcknowledge
SUBNE a1, a1, lr ; 0/1/2 = NoAck/Error/Busy
USATNE a1, #2, a1 ; 4+ => 3 = Error
ADRNE lr, %FT05
LDRNEB a1, [lr, a1]
B %FT20
05
ASSERT (ErrorNumber_IIC_Error - ErrorNumber_IIC_NoAcknowledge) = 1
ASSERT (ErrorNumber_IIC_Busy - ErrorNumber_IIC_NoAcknowledge) = 2
DCB IICStatus_NoACK, IICStatus_Error, IICStatus_Busy, IICStatus_Error
ASSERT (ErrorNumber_IIC_Error - ErrorNumber_IIC_NoAcknowledge) = 1
ASSERT (ErrorNumber_IIC_Busy - ErrorNumber_IIC_NoAcknowledge) = 2
DCB IICStatus_NoACK, IICStatus_Error, IICStatus_Busy, IICStatus_Error
10
BL IIC_DoOp_Poll
BL IIC_DoOp_Poll
20
; In case of error, assume nothing got transferred at all
CMP a1, #IICStatus_Completed
LDREQ a4, [sp, #(3*4)+(2*4)] ; Clipped block 2 request size
MOVNE a4, #0
ADD sp, sp, #24 ; Junk the iic_transfer blocks
STR a1, [sp, #0] ; Propagate return code
LDR a3, [sp, #8]
STR a4, [a3] ; Actual transfer size
Pull "a1-a3,pc"
CMP a1, #IICStatus_Completed
LDREQ a4, [sp, #(3*4)+(2*4)] ; Clipped block 2 request size
MOVNE a4, #0
ADD sp, sp, #24 ; Junk the iic_transfer blocks
STR a1, [sp, #0] ; Propagate return code
LDR a3, [sp, #8]
STR a4, [a3] ; Actual transfer size
Pull "a1-a3,pc"
IIC_DoOp_Poll
; IIC transfer function that performs a polling transfer, similar to HAL_VideoIICOp
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment