Commit f9184a7b authored by Jeffrey Lee's avatar Jeffrey Lee
Browse files

Initial SMP support

Detail:
  s/DBell, Makefile - Implement doorbell device
  s/Boot - Implement new SMP-related HAL entry points
  s/Interrupts - Remove DebugInterrupts code to make things easier to follow. Add a couple of macros for mapping IRQ numbers to register bits, to help deal with IRQ number translation. Implement new IRQ-related HAL entry points.
  hdr/omap4_reg - Offset the peripheral interrupt numbers so that 0-31 are core 0 private, 32-63 core 1 private, 64+ = peripheral
  hdr/StaticWS - Remove DebugInterrupts code. Reserve space for doorbell device.
  hdr/omap4430 - Remove DebugInterrupts code. Add definitions for aux core boot registers.
Admin:
  Tested on PandaBoard Rev A6


Version 0.52, 1.52.2.1. Tagged as 'OMAP4-0_52-1_52_2_1'
parent b4214424
......@@ -17,7 +17,7 @@
COMPONENT = OMAP-4 HAL
TARGET = OMAP4
OBJS = Top Boot Interrupts Timers CLib CLibAsm UART Debug PRCM Video USB I2C RTC SDMA TPS Audio GPIO GPMC NVMemory KbdScan SDIO SR44x PowerCtrl PL310
OBJS = Top Boot Interrupts Timers CLib CLibAsm UART Debug PRCM Video USB I2C RTC SDMA TPS Audio GPIO GPMC NVMemory KbdScan SDIO SR44x PowerCtrl PL310 DBell
USBDIR = <Lib$Dir>.USB
HDRS =
......
......@@ -5,19 +5,19 @@
*
*/
#define Module_MajorVersion_CMHG 0.52
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 10 May 2016
#define Module_MinorVersion_CMHG 1.52.2.1
#define Module_Date_CMHG 29 Jul 2017
#define Module_MajorVersion "0.52"
#define Module_Version 52
#define Module_MinorVersion ""
#define Module_Date "10 May 2016"
#define Module_MinorVersion "1.52.2.1"
#define Module_Date "29 Jul 2017"
#define Module_ApplicationDate "10-May-16"
#define Module_ApplicationDate "29-Jul-17"
#define Module_ComponentName "OMAP4"
#define Module_ComponentPath "castle/RiscOS/Sources/HAL/OMAP4"
#define Module_FullVersion "0.52"
#define Module_HelpVersion "0.52 (10 May 2016)"
#define Module_FullVersion "0.52 (1.52.2.1)"
#define Module_HelpVersion "0.52 (29 Jul 2017) 1.52.2.1"
#define Module_LibraryVersionInfo "0:52"
......@@ -26,6 +26,7 @@
GET Hdr:SDHCIDevice
GET Hdr:RTCDevice
GET Hdr:GPIODevice
GET Hdr:DBellDevice
sb RN 9
......@@ -98,14 +99,6 @@ L4_GPIO6_Log # 4 ; L4_GPIO6 base address
MaxI2CControllers * 4
I2C_Table # (MaxI2CControllers*I2CBlockSize) ; I2C HW ptrs & transfer states
[ DebugInterrupts
LastInterrupt_IRQ # 4 ; Last IRQ, -1 if cleared
LastInterrupt_FIQ # 4 ; Last FIQ, -1 if cleared
[ ExtraDebugInterrupts
ExtraDebugIRQEnabled # 4 ; Nonzero if extra debugging enabled
]
]
UARTFCRSoftCopy # 4
NCNBWorkspace # 4 ; Base of ncnb workspace
NCNBAllocNext # 4 ; next free address in ncnb workspace
......@@ -127,6 +120,7 @@ RTCWS # RTCSize
SDIOWS # SDHCISize * MaxSDControllers
PL310Device # HALDeviceSize
DBellDevice # HALDevice_DBell_Size
; align on 16 byte boundary
# (((:INDEX:@)+15):AND::NOT:15)-(:INDEX:@)
......
......@@ -32,17 +32,6 @@ CacheOff SETL {FALSE}
GBLL QEMU
QEMU SETL {FALSE}
; Interrupt debugging - warn over serial port when IRQSource/FIQSource is called twice
; in a row without IRQClear/FIQClear being called inbetween
GBLL DebugInterrupts
DebugInterrupts SETL Debug :LAND: {TRUE}
; Extra interrupt debugging - when a missed IRQClear is detected, enables code that
; prints a trace of IRQClear and IRQSource calls.
; Note: Doesn't track FIQs at the moment!
GBLL ExtraDebugInterrupts
ExtraDebugInterrupts SETL DebugInterrupts :LAND: {FALSE}
; Physical memory map. All unmentioned ranges are reserved.
; 00000000-3FFFFFFF GPMC
......@@ -106,6 +95,9 @@ CORTEXA9_CPU0 * &48243400
CORTEXA9_CPU1 * &48243800
CORTEXA9_WUGEN * &48281000
AUX_CORE_BOOT_0 * CORTEXA9_WUGEN + &800
AUX_CORE_BOOT_1 * CORTEXA9_WUGEN + &804
MPU_INTC * MPU_SCU
MPU_INTC_CPU * (MPU_GIC_PI - MPU_SCU)
MPU_INTC_DIST * (MPU_GIC_ID - MPU_SCU)
......
......@@ -42,11 +42,14 @@
; legacy mode (else treated like other interrupts lines with ID28
; and ID31 respectively)
; - 128 hardware interrupts: ID[159:32] (rising-edge or high-level sensitive).
; - We remap the interrupts so that RISC OS sees interrupts 0-31 as the core
; 0 private interrupts, 32-63 as the core 1 private interrupts, and 64-159
; as the shared interrupts.
;
MACRO
$lab OMAP44XX_HARDIRQ $x
$lab * 32 + $x
$lab * 64 + $x
MEND
OMAP44XX_IRQ_L2_CACHE OMAP44XX_HARDIRQ 0 ; L2 cache controller interrupt
......
......@@ -163,6 +163,7 @@ HALdescriptor DATA
IMPORT NVMemory_Init
IMPORT NVMemory_InitDevice
IMPORT PL310_InitDevice
IMPORT DBell_InitDevices
EXPORT Board_InitDevices_None
EXPORT Board_InitDevices_Panda
......@@ -179,6 +180,9 @@ HALdescriptor DATA
IMPORT HAL_FIQSource
IMPORT HAL_FIQStatus
IMPORT HAL_IRQMax
IMPORT HAL_IRQProperties
IMPORT HAL_IRQSetCores
IMPORT HAL_IRQGetCores
IMPORT HAL_Timers
IMPORT HAL_TimerDevice
......@@ -302,13 +306,12 @@ HAL_EntryTable DATA
NullEntry ; HAL_VideoBufferAlignment
NullEntry ; HAL_VideoOutputFormat
NullEntry ; HAL_MatrixColumns
NullEntry ; HAL_MatrixScan
NullEntry ; HAL_TouchscreenType
NullEntry ; HAL_TouchscreenRead
NullEntry ; HAL_TouchscreenMode
NullEntry ; HAL_TouchscreenMeasure
HALEntry HAL_IRQProperties
HALEntry HAL_IRQSetCores
HALEntry HAL_IRQGetCores
HALEntry HAL_CPUCount
HALEntry HAL_CPUNumber
HALEntry HAL_SMPStartup
HALEntry HAL_MachineID
......@@ -708,6 +711,7 @@ HAL_InitDevices
BL Audio_Init
BL PowerCtrl_Init
BL PL310_InitDevice
BL DBell_InitDevices
; Board-specific HAL devices
LDR pc, [sb, #BoardConfig_InitDevices]
Board_InitDevices_None
......@@ -867,6 +871,32 @@ HAL_Reset
DebugTX "HAL_Reset failed!"
B . ; Just in case
; Out: a1 = number of CPU cores
HAL_CPUCount
MOV a1, #2
MOV pc, lr
; Out: a1 = number of this core
HAL_CPUNumber
MRC p15, 0, a1, c0, c0, 5
AND a1, a1, #1
MOV pc, lr
; In: a1 = core number
; a2 = boot physical address
; Out: Indicated core will be booting (undefined if a1 is current core)
; Assume caller has fully flushed the boot code to RAM (no DSB prior to mbox write)
HAL_SMPStartup
LDR a3, L4_Per_Log
LDR a4, =AUX_CORE_BOOT_1-L4_Per
STR a2, [a3, a4]!
DMB
MOV a4, #-1
STR a4, [a3, #AUX_CORE_BOOT_0-AUX_CORE_BOOT_1]
DSB
SEV
MOV pc, lr
LTORG
EXPORT vtophys
......
;
; Copyright (c) 2016, RISC OS Open Ltd
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of RISC OS Open Ltd nor the names of its contributors
; may be used to endorse or promote products derived from this software
; without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
;
IMPORT memcpy
GET Hdr:ListOpts
GET Hdr:CPU.Arch
GET Hdr:Macros
GET Hdr:Proc
GET Hdr:OSEntries
GET hdr.omap4430
GET hdr.StaticWS
GET hdr.Interrupts
sb RN 9
EXPORT DBell_InitDevices
AREA |Asm$$Code|, CODE, READONLY, PIC
DBell_InitDevices ROUT
Entry
ADRL a1, DBellDevice
ADR a2, DBellTemplate
MOV a3, #HALDevice_DBell_Size
BL memcpy
ADRL a2, DBellDevice
LDR a1, MPU_INTC_Log
STR a1, [a2, #HALDevice_Address]
MOV a1, #0
MOV lr, pc
LDR pc, OSentries+4*OS_AddDevice
EXIT
MACRO
$class HALDeviceField $field, $value
LCLS myvalue
[ "$value" = ""
myvalue SETS "$field"
|
myvalue SETS "$value"
]
ASSERT . - %A0 = HALDevice_$class$field
[ ?HALDevice_$class$field = 2
DCW $myvalue
ELIF ?HALDevice_$class$field = 4
DCD $myvalue
|
% ?HALDevice_$class$field
]
MEND
DBellTemplate
0
HALDeviceField Type, HALDeviceType_Comms + HALDeviceComms_ARMDBell
HALDeviceField ID, HALDeviceID_ARMDBell_GIC
HALDeviceField Location, HALDeviceBus_Sys + HALDeviceSysBus_AXI
HALDeviceField Version, 0
HALDeviceField Description, DBell_Description
HALDeviceField Address, 0
HALDeviceField Reserved1, 0
HALDeviceField Activate, DBell_Activate
HALDeviceField Deactivate, DBell_Deactivate
HALDeviceField Reset, DBell_Reset
HALDeviceField Sleep, DBell_Sleep
HALDeviceField Device, -1 ; IRQ numbers vary by core, use DBell_GetIRQ
HALDeviceField TestIRQ, DBell_TestIRQ
HALDeviceField ClearIRQ, DBell_ClearIRQ
HALDeviceField Reserved2, 0
ASSERT . - %A0 = HALDeviceSize
DBell HALDeviceField GetIRQ, DBell_GetIRQ
DBell HALDeviceField Ring, DBell_Ring
ASSERT . - %A0 = HALDevice_DBell_Size
DBell_Description
DCB "GIC SGI doorbell", 0
ALIGN
DBell_Activate
DBell_TestIRQ
MOV a1, #1
DBell_Deactivate
DBell_Reset
MOV pc, lr
DBell_Sleep
MOV a1, #0
MOV pc, lr
DBell_GetIRQ
; In: a2 = core number
MOV a1, a2, LSL #5 ; IRQ 0???
MOV pc, lr
DBell_ClearIRQ
MOV pc, lr
DBell_Ring
; In: a2 = mask of CPU cores
LDR a1, [a1, #HALDevice_Address]
MOV a2, a2, LSL #16
ADD a1, a1, #MPU_INTC_DIST
STR a2, [a1, #GIC_DIST_SOFTINT]
MOV pc, lr
END
......@@ -20,6 +20,7 @@
GET Hdr:ImageSize.<ImageSize>
GET Hdr:OSEntries
GET Hdr:HALEntries
GET hdr.omap4430
GET hdr.StaticWS
......@@ -40,12 +41,32 @@
EXPORT HAL_FIQSource
EXPORT HAL_FIQStatus
EXPORT HAL_IRQMax
EXPORT HAL_IRQProperties
EXPORT HAL_IRQSetCores
EXPORT HAL_IRQGetCores
; Debug flag to cause the DebugInterrupts noncleared IRQ detection code to disable the source
; of the noncleared interrupt. This can be useful in debugging issues that cause the
; nonclearance of the IRQ, e.g. if an IRQ handler aborts before it's able to call IRQClear.
GBLL DebugDisablePrevious
DebugDisablePrevious SETL {FALSE}
; $base += ($num >> 5) << 2
; $bit = 1 << ($num & 31)
; NE if $num >= 32
; $temp can be $num
MACRO
BitMap $num, $base, $bit, $temp
MOVS $bit, $num, LSR #5
AND $temp, $num, #31
ADD $base, $base, $bit, LSL #2
MOV $bit, #1
MOV $bit, $bit, LSL $temp
MEND
; As above, but $base = ($num >> 5) << 2
MACRO
BitMap0 $num, $base, $bit, $temp
MOVS $base, $num, LSR #5
AND $temp, $num, #31
MOV $base, $base, LSL #2
MOV $bit, #1
MOV $bit, $bit, LSL $temp
MEND
Interrupt_Init
; 1. disable Distributor Controller
......@@ -57,7 +78,7 @@ Interrupt_Init
; 2. set all global interrupts to be level triggered, active low
ADD a3, a1, #GIC_DIST_CONFIG
ADD a3, a3, #8
MOV a4, #INTERRUPT_MAX
MOV a4, #INTERRUPT_MAX-32
MOV ip, #32
10
STR a2, [a3], #4
......@@ -112,155 +133,73 @@ Interrupt_Init
MOV a2, #ICCICR_ENABLE
STR a2, [a1, #(MPU_INTC_CPU + GIC_CPU_CTRL)]
; ... and everything else looks good?
[ DebugInterrupts
MOV a1, #-1
STR a1, LastInterrupt_IRQ
STR a1, LastInterrupt_FIQ
[ ExtraDebugInterrupts
MOV a1, #0
STR a1, ExtraDebugIRQEnabled
]
]
MOV pc, lr
HAL_IRQEnable
HAL_IRQEnable ROUT
CMP a1, #INTERRUPT_MAX
MOVHS a1, #0
MOVHS pc, lr
; Disable interrupts while we update the controller
MRS a4, CPSR
ORR a3, a4, #F32_bit+I32_bit
MSR CPSR_c, a3
; Unmask the interrupt
LDR a3, MPU_INTC_Log
ADD ip, a3, #(MPU_INTC_DIST + GIC_DIST_ENABLE_SET)
AND a2, a1, #31 ; bit = intno % 32
MOV a1, a1, LSR #5 ; index = intno / 32
ADD ip, ip, a1, LSL #2
MOV a1, #1
MOV a2, a1, LSL a2 ; mask = (1 << bit)
LDR a1, [ip, #0] ; get old state
STR a2, [ip, #0] ; set new state
MSR CPSR_c, a4 ; Re-enable interrupts
AND a1, a1, a2 ; Test if it was enabled or not
BitMap0 a1, a2, a3, a4
CMP a1, #32
LDR a4, MPU_INTC_Log
SUBHS a2, a2, #4 ; Remap to GIC registers (assume we won't get called with wrong private interrupt)
ADD a4, a4, #MPU_INTC_DIST + GIC_DIST_ENABLE_SET
LDR a1, [a4, a2] ; Get old state
STR a3, [a4, a2] ; Set new state
AND a1, a1, a3 ; Return value
MOV pc, lr
HAL_IRQDisable
HAL_IRQDisable ROUT
CMP a1, #INTERRUPT_MAX
MOVHS a1, #0
MOVHS pc, lr
Push "lr"
; Disable interrupts while we update the controller
; (not necessarily needed for disabling them?)
MRS a4, CPSR
ORR a3, a4, #F32_bit+I32_bit
MSR CPSR_c, a3
; Now mask the interrupt
LDR a3, MPU_INTC_Log
ADD ip, a3, #(MPU_INTC_DIST + GIC_DIST_ENABLE_CLEAR)
AND a2, a1, #31 ; bit = intno % 32
MOV lr, a1, LSR #5 ; index = intno / 32
ADD ip, ip, lr, LSL #2
MOV lr, #1
MOV a2, lr, LSL a2 ; mask = (1 << bit)
LDR lr, [ip, #0] ; get old state
STR a2, [ip, #0] ; mask the interrupt
[ {FALSE} ; reading GIC_CPU_INTACK has side effects on the interrupt system !?
; Check if we just disabled the active interrupt
LDR ip, [a3, #(MPU_INTC_CPU + GIC_CPU_INTACK)]
CMP ip, a1
STREQ ip, [a3, #(MPU_INTC_CPU + GIC_CPU_EOI)]
[ DebugInterrupts
MOVEQ ip, #-1
STREQ ip, LastInterrupt_IRQ
]
|
; Clear any pending state of this source
STR a2, [ip, #(GIC_DIST_PENDING_CLEAR - GIC_DIST_ENABLE_CLEAR)]
; Was it active?
LDR ip, [ip, #(GIC_DIST_ACTIVE_BIT - GIC_DIST_ENABLE_CLEAR)]
TST ip, a2
STRNE a1, [a3, #(MPU_INTC_CPU + GIC_CPU_EOI)]
[ DebugInterrupts
MOVNE ip, #-1
STRNE ip, LastInterrupt_IRQ
]
]
MSR CPSR_c, a4 ; Re-enable interrupts
AND a1, lr, a2 ; Test if it was enabled or not
Pull "pc"
BitMap0 a1, a2, a3, a4
CMP a1, #32
LDR ip, MPU_INTC_Log
SUBHS a2, a2, #4 ; Remap to GIC registers (assume we won't get called with wrong private interrupt)
ADD a4, ip, #MPU_INTC_DIST + GIC_DIST_ENABLE_CLEAR
LDR a2, [a4, a2]! ; Get old state
STR a3, [a4] ; Set new state
LDR a4, [a4, #GIC_DIST_ACTIVE_BIT-GIC_DIST_ENABLE_CLEAR] ; TODO could this be bogus? - if register isn't banked we'll do the wrong thing
SUBHS a1, a1, #32
TST a4, a3 ; Was it active?
BEQ %FT90
CMPLO a1, #16 ; LO if this is core 0 private, check to see if SGI
ORRLO a1, a1, #1<<10 ; Set opposite to current CPU
STR a1, [ip, #(MPU_INTC_CPU + GIC_CPU_EOI)]
90
AND a1, a2, a3 ; Return value
DSB SY
MOV pc, lr
HAL_IRQClear
[ ExtraDebugInterrupts
LDR a2, ExtraDebugIRQEnabled
CMP a2, #0
BEQ %FT10
Push "lr"
DebugReg a1, "HAL_IRQClear: "
Pull "lr"
10
]
HAL_IRQClear ROUT
CMP a1, #32
SUBHS a1, a1, #32 ; Map to GIC interrupt number
; Signal End Of Interrupt
CMP a1, #16 ; SGI?
BHS %FT10
MRC p15, 0, a2, c0, c0, 5
TST a2, #1
ADDEQ a1, a1, #1<<10 ; Assume it came from the other CPU
10
LDR a2, MPU_INTC_Log
STR a1, [a2, #(MPU_INTC_CPU + GIC_CPU_EOI)]
; Data synchronisation barrier to make sure INTC gets the message
DSB SY
[ DebugInterrupts
MOV a1, #-1
STR a1, LastInterrupt_IRQ
]
MOV pc, lr
HAL_IRQSource
[ DebugInterrupts
LDR a1, LastInterrupt_IRQ
CMP a1, #0
BLT %FT10
Push "lr"
BL DebugHALPrint
= "HAL_IRQSource: Previous IRQ not cleared: ", 0
DebugReg a1
[ DebugDisablePrevious
BL HAL_IRQDisable
]
[ ExtraDebugInterrupts
[ :LNOT: DebugDisablePrevious ; Doesn't play nice with this since it'll just spam the HAL_IRQClear messages
STR pc, ExtraDebugIRQEnabled ; any nonzero value will do
]
MOV lr, pc ; BL to the main routine so we can get the exit code
B %FT05
DebugReg a1, "HAL_IRQSource: New IRQ: "
Pull "pc"
05
|
Pull "lr"
]
10
]
; Does the ARM think an interrupt is occuring?
MRC p15, 0, a1, c12, c1, 0
TST a1, #I32_bit
MOVEQ a1, #-1
[ DebugInterrupts
STREQ a1, LastInterrupt_IRQ
]
MOVEQ pc, lr
HAL_IRQSource ROUT
LDR a2, MPU_INTC_Log
LDR a3, [a2, #(MPU_INTC_CPU + GIC_CPU_INTACK)]
BIC a1, a3, #ICCIAR_CPUID
CMP a1, #INTERRUPT_MAX
[ DebugInterrupts
STRLO a1, LastInterrupt_IRQ
]
MOVLO pc, lr
; Authentic spurious interrupt - restart INTC and return -1
STR a3, [a2, #(MPU_INTC_CPU + GIC_CPU_EOI)]
; Data synchronisation barrier to make sure INTC gets the message
DSB SY
MOV a1, #-1
[ DebugInterrupts
STR a1, LastInterrupt_IRQ
]
CMP a1, #INTERRUPT_MAX-32
MOVHI a1, #-1 ; Spurious interrupt, ignore it
MOVHI pc, lr
MRC p15, 0, a4, c0, c0, 5
AND a4, a4, #1
CMP a1, #32
ADDLO a1, a1, a4, LSL #5 ; Remap private interrupt
ADDHS a1, a1, #32 ; Remap shared interrupt
MOV pc, lr
HAL_IRQStatus
......@@ -268,15 +207,12 @@ HAL_IRQStatus
CMP a1, #INTERRUPT_MAX
MOVHS a1, #0
MOVHS pc, lr
LDR a2, MPU_INTC_Log
ADD ip, a2, #(MPU_INTC_DIST + GIC_DIST_ACTIVE_BIT)
MOV a3, a1, LSR #5 ; index = intno / 32
ADD ip, ip, a3, LSL #2
LDR a3, [ip, #0] ; get old state
AND a1, a1, #31 ; bit = intno % 32
MOV a1, a3, LSR a1 ; Shift and invert so 1=active
AND a1, a1, #1 ; 0 = not firing, 1 = firing
ADD a2, a2, #(MPU_INTC_DIST + GIC_DIST_ACTIVE_BIT)
BitMap a1, a2, a3, a4
SUBNE a2, a2, #4 ; Remap to GIC registers
LDR a1, [a2] ; Get status
AND a1, a1, a3
MOV pc, lr
......@@ -353,10 +289,6 @@ HAL_FIQDisable
CMP ip, a1
MOVEQ ip, #2
STREQ ip, [a3, #INTCPS_CONTROL]
[ DebugInterrupts
MOVEQ ip, #-1
STREQ ip, LastInterrupt_FIQ
]
MSR CPSR_c, a4 ; Re-enable interrupts
BIC a1, a2, lr ; Clear the masked interrupts from a2 to get nonzero result if it was enabled
Pull "pc"
......@@ -414,10 +346,6 @@ HAL_FIQDisableAll_Loop3
STR a1, [a2, #INTCPS_CONTROL]
; Data synchronisation barrier to make sure INTC gets the message
DSB SY
[ DebugInterrupts
MOV a1, #-1
STR a1, LastInterrupt_FIQ
]
] ; FIQ_Supported
MOV pc, lr
......@@ -429,10 +357,6 @@ HAL_FIQClear
STR a1, [a2, #INTCPS_CONTROL]
; Data synchronisation barrier to make sure INTC gets the message
DSB SY
[ DebugInterrupts
MOV a1, #-1
STR a1, LastInterrupt_FIQ
]
] ; FIQ_Supported
MOV pc, lr
......@@ -471,38 +395,18 @@ HAL_FIQStatus
HAL_FIQSource
[ FIQ_Supported
[ DebugInterrupts
LDR a1, LastInterrupt_FIQ
CMP a1, #0
BLT %FT10