Commit f8acd505 authored by Robert Sprowson's avatar Robert Sprowson
Browse files

Changes for OMAP4 HAL

hdr/GPIO: aligned columns
hdr/USB: added more USB related register definitions (OTG and USBPHY)
hdr/Video: global variable for preventing multiple inclusion renamed to its original
hdr/irqs44xx: interrupt numbers and naming according to latest OMAP44xx TRMs
hdr/omap4430: address correction for L4_USBPHY
s/Audio:
    changed recovering from error conditions
    disabled kludge for supporting non native samplerates (44.1 + 48k)
s/PRCM:
    removed unused function PRCM_GetFreqSel and related table
s/SDIO
    aligned columns
s/USB
    name change for OTG interrupt source

Part of a number of changes from Willi Theiss.
Build, but not tested.

Version 0.14. Tagged as 'OMAP4-0_14'
parent e198fedf
/* (0.13)
/* (0.14)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.13
#define Module_MajorVersion_CMHG 0.14
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 22 Jan 2013
#define Module_Date_CMHG 07 Apr 2013
#define Module_MajorVersion "0.13"
#define Module_Version 13
#define Module_MajorVersion "0.14"
#define Module_Version 14
#define Module_MinorVersion ""
#define Module_Date "22 Jan 2013"
#define Module_Date "07 Apr 2013"
#define Module_ApplicationDate "22-Jan-13"
#define Module_ApplicationDate "07-Apr-13"
#define Module_ComponentName "OMAP4"
#define Module_ComponentPath "castle/RiscOS/Sources/HAL/OMAP4"
#define Module_FullVersion "0.13"
#define Module_HelpVersion "0.13 (22 Jan 2013)"
#define Module_LibraryVersionInfo "0:13"
#define Module_FullVersion "0.14"
#define Module_HelpVersion "0.14 (07 Apr 2013)"
#define Module_LibraryVersionInfo "0:14"
......@@ -20,55 +20,55 @@
; GPIO registers - relative to L4_GPIO1, L4_GPIO2, L4_GPIO3, etc.
GPIO_REVISION * &000
GPIO_SYSCONFIG * &010
GPIO_IRQSTATUS_RAW_0 * &024
GPIO_IRQSTATUS_RAW_1 * &028
GPIO_IRQSTATUS_0 * &02C
GPIO_IRQSTATUS_1 * &030
GPIO_IRQSTATUS_SET_0 * &034
GPIO_IRQSTATUS_SET_1 * &038
GPIO_IRQSTATUS_CLR_0 * &03C
GPIO_IRQSTATUS_CLR_1 * &040
GPIO_IRQWAKEN_0 * &044
GPIO_IRQWAKEN_1 * &048
GPIO_SYSTATUS * &114
GPIO_IRQSTATUS1 * &118
GPIO_IRQENABLE1 * &11C
GPIO_WAKEUPENABLE * &120
GPIO_IRQSTATUS2 * &128
GPIO_IRQENABLE2 * &12C
GPIO_CTRL * &130
GPIO_OE * &134
GPIO_DATAIN * &138
GPIO_DATAOUT * &13C
GPIO_LEVELDETECT0 * &140
GPIO_LEVELDETECT1 * &144
GPIO_RISINGDETECT * &148
GPIO_FALLINGDETECT * &14C
GPIO_DEBOUNCEENABLE * &150
GPIO_DEBOUNCINGTIME * &154
GPIO_CLEARIRQENABLE1 * &160
GPIO_SETIRQENABLE1 * &164
GPIO_CLEARIRQENABLE2 * &170
GPIO_SETIRQENABLE2 * &174
GPIO_CLEARWKUPENA * &180
GPIO_SETWKUENA * &184
GPIO_CLEARDATAOUT * &190
GPIO_SETDATAOUT * &194
GPIO_PIN_MAX * 192
GPIO_REVISION * &000
GPIO_SYSCONFIG * &010
GPIO_IRQSTATUS_RAW_0 * &024
GPIO_IRQSTATUS_RAW_1 * &028
GPIO_IRQSTATUS_0 * &02C
GPIO_IRQSTATUS_1 * &030
GPIO_IRQSTATUS_SET_0 * &034
GPIO_IRQSTATUS_SET_1 * &038
GPIO_IRQSTATUS_CLR_0 * &03C
GPIO_IRQSTATUS_CLR_1 * &040
GPIO_IRQWAKEN_0 * &044
GPIO_IRQWAKEN_1 * &048
GPIO_SYSTATUS * &114
GPIO_IRQSTATUS1 * &118
GPIO_IRQENABLE1 * &11C
GPIO_WAKEUPENABLE * &120
GPIO_IRQSTATUS2 * &128
GPIO_IRQENABLE2 * &12C
GPIO_CTRL * &130
GPIO_OE * &134
GPIO_DATAIN * &138
GPIO_DATAOUT * &13C
GPIO_LEVELDETECT0 * &140
GPIO_LEVELDETECT1 * &144
GPIO_RISINGDETECT * &148
GPIO_FALLINGDETECT * &14C
GPIO_DEBOUNCEENABLE * &150
GPIO_DEBOUNCINGTIME * &154
GPIO_CLEARIRQENABLE1 * &160
GPIO_SETIRQENABLE1 * &164
GPIO_CLEARIRQENABLE2 * &170
GPIO_SETIRQENABLE2 * &174
GPIO_CLEARWKUPENA * &180
GPIO_SETWKUENA * &184
GPIO_CLEARDATAOUT * &190
GPIO_SETDATAOUT * &194
GPIO_PIN_MAX * 192
; Flags for GPIOx_SetAndEnableIRQ
GPIO_LEVELDETECT0_FLAG * 1
GPIO_LEVELDETECT1_FLAG * 2
GPIO_RISINGDETECT_FLAG * 4
GPIO_FALLINGDETECT_FLAG * 8
GPIO_LEVELDETECT0_FLAG * 1
GPIO_LEVELDETECT1_FLAG * 2
GPIO_RISINGDETECT_FLAG * 4
GPIO_FALLINGDETECT_FLAG * 8
; interrupt number of lowest GPIO port
GPIO1_IRQ_NO * OMAP44XX_IRQ_GPIO1
GPIO1_IRQ_NO * OMAP44XX_IRQ_GPIO1
; TWL/TPS GPIO registers
......@@ -135,16 +135,16 @@ TPS_LED_PIN_MAX * 2
MACRO
GPIO_PrepareR $regs, $mask, $num, $cc, $tmp
ASSERT $regs <> $mask
[ "$tmp" = ""
[ "$tmp" = ""
ASSERT $mask <> $num
[ $regs = $num
[ $regs = $num
EOR$cc $num, $num, #31
MOV$cc $mask, #&80000000
MOV$cc $mask, $mask, ROR $num
MOV$cc $regs, $num, LSR #5
ADD$cc $regs, sb, $regs, LSL #2
LDR$cc $regs, [$regs, #:INDEX:L4_GPIO_Table]
|
|
; Slightly better instruction ordering
MOV$cc $regs, $num, LSR #5
EOR$cc $num, $num, #31
......@@ -152,8 +152,8 @@ TPS_LED_PIN_MAX * 2
MOV$cc $mask, #&80000000
LDR$cc $regs, [$regs, #:INDEX:L4_GPIO_Table]
MOV$cc $mask, $mask, ROR $num
]
|
]
|
ASSERT $mask <> $tmp
ASSERT $regs <> $tmp
ASSERT $num <> $tmp ; no point using $tmp if the two are the same!
......@@ -164,7 +164,7 @@ TPS_LED_PIN_MAX * 2
MOV$cc $mask, #&80000000
LDR$cc $regs, [$regs, #:INDEX:L4_GPIO_Table]
MOV$cc $mask, $mask, ROR $num
]
]
MEND
; Set pin for output
......
......@@ -157,6 +157,49 @@ EHCI_INSNREG06 * &00A8
EHCI_INSNREG07 * &00AC
EHCI_INSNREG08 * &00B0
; OTG registers - relative to L4_USB_OTG
OTG_BASE * &0400
; OTG registers - relative to OTG_BASE
OTG_REVISION * &0000
OTG_SYSCONFIG * &0004
OTG_SYSSTATUS * &0008
OTG_INTERFSEL * &000C
OTG_SIMENABLE * &0010
OTG_FORCESTDBY * &0014
OTG_BIGENDIAN * &0018
; OCP2SCP registers - relative to L4_USBPHY
OCP2SCP_REVISION * &0000
OCP2SCP_SYSCONFIG * &0010
OCP2SCP_SYSSTATUS * &0014
OCP2SCP_TIMING * &0018
; USBPHY registers - relative to L4_USBPHY
USBPHY_BASE * &0080
; USBPHY registers - relative to USBPHY_BASE
USBPHY_TERMINATION_CONTROL * &0000
USBPHY_RX_CALIB * &0004
USBPHY_DLLHS_2 * &0008
USBPHY_RX_TEST_2 * &000C
USBPHY_TX_TEST_CHRG_DET * &0010
USBPHY_CHRG_DET * &0014
USBPHY_PWR_CNTL * &0018
USBPHY_UTMI_INTERFACE_CNTL_1 * &001C
USBPHY_UTMI_INTERFACE_CNTL_2 * &0020
USBPHY_BIST * &0024
USBPHY_BIST_CRC * &0028
USBPHY_CDR_BIST2 * &002C
USBPHY_GPIO * &0030
USBPHY_DLLHS * &0034
USBPHY_USB2PHYCM_TRIM * &0038
USBPHY_USB2PHYCM_CONFIG * &003C
USBPHY_USBOTG * &0040
USBPHY_AD_INTERFACE_REG1 * &0044
USBPHY_AD_INTERFACE_REG2 * &0048
USBPHY_AD_INTERFACE_REG3 * &004C
USBPHY_ANA_CONFIG1 * &0050
USBPHY_ANA_CONFIG2 * &0054
] ; __HAL_USB_HDR__
......
......@@ -13,8 +13,8 @@
; limitations under the License.
;
[ :LNOT: :DEF: __HAL_VideoHDR__
GBLL __HAL_VideoHDR__
[ :LNOT: :DEF: __HAL_VIDEO_HDR__
GBLL __HAL_VIDEO_HDR__
GET hdr.irqs44xx
......@@ -565,6 +565,6 @@ VideoDeviceDevice # HALDevice_VDU_Size
VideoWorkspace # 4 ; HAL workspace pointer
Video_DeviceSize * :INDEX: @
] ; __HAL_VideoHDR__
] ; __HAL_VIDEO_HDR__
END
......@@ -49,8 +49,8 @@ OMAP44XX_IRQ_PL310 * (0 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_CTI0 * (1 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_CTI1 * (2 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_ELM * (4 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_CMU * (5 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_SYS_1N * (7 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_SECURITY_EVENTS * (8 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_L3_DBG * (9 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_L3_APP * (10 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_PRCM * (11 + OMAP44XX_IRQ_GIC_START)
......@@ -60,24 +60,23 @@ OMAP44XX_IRQ_SDMA_2 * (14 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_SDMA_3 * (15 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_MCBSP4 * (16 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_MCBSP1 * (17 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_SR_MCU * (18 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_SR_MPU * (18 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_SR_CORE * (19 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_GPMC * (20 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_GFX * (21 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_SGX * (21 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_MCBSP2 * (22 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_MCBSP3 * (23 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_ISS_5 * (24 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_DSS_DISPC * (25 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_MAIL_U0 * (26 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_C2C_SSCM_0 * (27 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_TESLA_MMU * (28 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_DSP_MMU * (28 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_GPIO1 * (29 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_GPIO2 * (30 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_GPIO3 * (31 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_GPIO4 * (32 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_GPIO5 * (33 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_GPIO6 * (34 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_USIM * (35 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_WDT3 * (36 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_GPT1 * (37 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_GPT2 * (38 + OMAP44XX_IRQ_GIC_START)
......@@ -90,11 +89,7 @@ OMAP44XX_IRQ_GPT8 * (44 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_GPT9 * (45 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_GPT10 * (46 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_GPT11 * (47 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_SPI4 * (48 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_SHA1_S * (49 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_FPKA_SINTREQUEST_S * (50 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_SHA1_P * (51 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_RNG * (52 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_MCSPI4 * (48 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_DSS_DSI1 * (53 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_I2C1 * (56 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_I2C2 * (57 + OMAP44XX_IRQ_GIC_START)
......@@ -102,10 +97,8 @@ OMAP44XX_IRQ_HDQ * (58 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_MMC5 * (59 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_I2C3 * (61 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_I2C4 * (62 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_AES2_S * (63 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_AES2_P * (64 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_SPI1 * (65 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_SPI2 * (66 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_MCSPI1 * (65 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_MCSPI2 * (66 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_HSI_P1 * (67 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_HSI_P2 * (68 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_FDIF_3 * (69 + OMAP44XX_IRQ_GIC_START)
......@@ -115,50 +108,40 @@ OMAP44XX_IRQ_UART1 * (72 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_UART2 * (73 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_UART3 * (74 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_PBIAS * (75 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_OHCI * (76 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_EHCI * (77 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_TLL * (78 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_AES1_S * (79 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_HSUSB_OHCI * (76 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_HSUSB_EHCI * (77 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_HSUSB_TLL * (78 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_WDT2 * (80 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_DES_S * (81 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_DES_P * (82 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_MMC1 * (83 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_DSS_DSI2 * (84 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_AES1_P * (85 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_MMC2 * (86 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_MPU_ICR * (87 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_C2C_SSCM_1 * (88 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_FSUSB * (89 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_FSUSB_SMI * (90 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_SPI3 * (91 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_HS_USB_MC_N * (92 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_HS_USB_DMA_N * (93 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_MCSPI3 * (91 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_HSUSB_OTG * (92 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_HSUSB_OTG_DMA * (93 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_MMC3 * (94 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_GPT12 * (95 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_MMC4 * (96 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_SLIMBUS1 * (97 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_SLIMBUS2 * (98 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_ABE * (99 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_DUCATI_MMU * (100 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_CORTEXM3_MMU * (100 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_DSS_HDMI * (101 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_SR_IVA * (102 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_IVA_HD_POSYNCITRPEND_1 * (103 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_IVA_HD_POSYNCITRPEND_0 * (104 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_IVA_HD_POMBINTRPEND_0 * (107 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_MCASP1_AR * (108 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_IVAHD_1 * (103 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_IVAHD_0 * (104 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_IVAHD_MAILBOX_0 * (107 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_MCASP1_AX * (109 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_EMIF4_1 * (110 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_EMIF4_2 * (111 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_EMIF1 * (110 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_EMIF2 * (111 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_MCPDM * (112 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_DMM * (113 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_DMIC * (114 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_CDMA_0 * (115 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_CDMA_1 * (116 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_CDMA_2 * (117 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_CDMA_3 * (118 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_SYS_2N * (119 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_KBD_CTL * (120 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_UNIPRO1 * (124 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_THERMAL_ALERT * (126 + OMAP44XX_IRQ_GIC_START)
] ; __HAL_IRQS44XX_HDR__
......
......@@ -125,12 +125,12 @@ L4_ClockMan2 * (L4_Core + &008000) ; Clock manager (module 2)
L4_sDMA * (L4_Core + &056000) ; sDMA config
L4_HSI * (L4_Core + &058000) ; HSI (top, DMA, port1, port2)
L4_SAR_ROM * (L4_Core + &05E000) ; SAR_ROM (save and restore)
L4_USBTLL * (L4_Core + &062000) ; HSUSBTLL thing
L4_USBTLL * (L4_Core + &062000) ; HSUSBTLL (transceiverless link)
L4_USB_Host * (L4_Core + &064000) ; USB host config (HSUSBHOST)
L4_DSP * (L4_Core + &066000) ; DSP subsystem
L4_FSUSB * (L4_Core + &0A9000) ; FSUSB config (Full Speed)
L4_USB_OTG * (L4_Core + &0AB000) ; USB OTG config (HSUSBOTG)
L4_USBPHY * (L4_Core + &0AD080) ; USBPHY config
L4_USBPHY * (L4_Core + &0AD000) ; USBPHY config
L4_SR_MPU * (L4_Core + &0D9000) ; SmartReflex MPU
L4_SR_IVA * (L4_Core + &0DB000) ; SmartReflex IVA
L4_SR_CORE * (L4_Core + &0DD000) ; SmartReflex Core
......
......@@ -177,20 +177,20 @@ AUDIO_POWER_DELAY * (50*1024) ; ~51 ms
;MCPDM_IRQ_DN_MASK * (MCPDM_IRQ_DN_EMPTY + MCPDM_IRQ_DN_FULL)
MCPDM_IRQ_DN_MASK * (MCPDM_IRQ_DN_FULL)
; flag for using only supported sample rates
GBLL AllSampleRates
AllSampleRates SETL {FALSE}
; flag to enable mono to stereo switching for headset
; ATM just for testing: it doubles the playrate because the right channel gets the same value
; as the left channel
; ToDo: how to map lower sample rates to the supported ones (88.2 | 96 kHz)?
GBLL Mono2Stereo
Mono2Stereo SETL {TRUE}
Mono2Stereo SETL {TRUE} :LAND: AllSampleRates
; McPDM downlink channel mask
MCPDM_DL_CHANNELS * (MCPDM_CTRL_PDM_DN1_EN + MCPDM_CTRL_PDM_DN2_EN)
; flag for using only supported sample rates
GBLL AllSampleRates
AllSampleRates SETL {FALSE}
; special gain values for marking OFF state
HS_GAIN_OFF * &F0
HF_GAIN_OFF * &1F
......@@ -382,8 +382,10 @@ ratetab
cdf 22050, 45, 1, MODE_1764 ; 22.05kHz (~45 us) CD/2
cdf 32000, 31, 1, MODE_1920 ; 32kHz (~31 us) AC97*2/3
] ; AllSampleRates
[ {FALSE} ; these are not natively supported
cdf 44100, 23, 1, MODE_1764 ; 44.1kHz (~23 us) CD/1
cdf 48000, 21, 1, MODE_1920 ; 48kHz (~21 us) AC97/1
]
cdf 88200, 11, 0, MODE_1764 ; 88.2kHz (~11 us) CD*2
cdf 96000, 10, 0, MODE_1920 ; 96kHz (~10 us) AC97*2
......@@ -503,7 +505,7 @@ AudioActivate
LDRB a3, [a3, #(6*8+5)] ; use 48 kHz rate
|
LDRB a4, [a3, #(1*8+6)]
LDRB a3, [a3, #(1*8+5)] ; use 48 kHz rate
LDRB a3, [a3, #(1*8+5)] ; use 96 kHz rate
] ; AllSampleRates
STRB a4, AudioMono
CMP a4, #0
......@@ -689,7 +691,7 @@ IRQHandle
DebugReg a2,"IRQHandle: IRQSTATUS="
Pull "sb,lr"
]
[ {FALSE}
[ {TRUE} ;{FALSE}
; Just clear the IRQ and ask for an audio reset
LDR a3, AudioRegs
MVN a2, #0
......
......@@ -32,16 +32,13 @@
IMPORT Timer_Init
EXPORT PRCM_SetClocks
EXPORT PRCM_GetFreqSel
PRCM_SetClocks
Push "v1-v4,lr"
; First we calculate the system clock speed by measuring it against the 32KHz counter
; Then we make sure all system clocks are set to max
; This is basically the same algorithm as u-boot uses
LDR v4, L4_PowerMan_Log
; Use timer 2, just so we don't have to worry about turning it off later (since it's used as HAL timer 0)
BL Timer_Init ; Just (re)initialise all of them for simplicity
Push "v1-v3,lr"
; We calculate the system clock speed by measuring it against the 32KHz counter
; Use HAL's 1st timer, just so we don't have to worry about turning it off later
; (since it's used as HAL timer 0)
BL Timer_Init ; Just (re)initialise all of them for simplicity
LDR a3, Timers_Log
MOV a1, #0
STR a1, [a3, #GPT_TLDR] ; Start at 0
......@@ -74,22 +71,7 @@ PRCM_SetClocks
BLE %BT10
STR a4, sys_clk
STR v3, Timer_DelayMul
Pull "v1-v4,pc"
PRCM_GetFreqSel
; Return PLL FREQSEL value for a given clock frequency
; In: a1=Fint
; Out: a1=FREQSEL, 0 for error
; Corrupts a2-a4,ip
ADR ip, FreqSelTable
10
LDMIA ip!, {a2-a4}
CMP a1, a2
CMPHS a3, a1
BLO %BT10
MOV a1, a4
MOV pc, lr
Pull "v1-v3,pc"
SysClkTable
; Counter Clock speed SYS_CLKSEL Divider DelayMul
......@@ -100,18 +82,4 @@ SysClkTable
DCD -1, 12000000, 0, 1, 120
; Where is 16.8MHz?
FreqSelTable
; Min rate Max rate FREQSEL value
DCD 750000, 1000000, &3
DCD 1000000, 1250000, &4
DCD 1250000, 1500000, &5
DCD 1500000, 1750000, &6
DCD 1750000, 2100000, &7
DCD 7500000, 10000000, &B
DCD 10000000, 12500000, &C
DCD 12500000, 15000000, &D
DCD 15000000, 17500000, &E
DCD 17500000, 21000000, &F
DCD 0, &FFFFFFFF, 0 ; List terminator is catch-all for error case
END
......@@ -85,11 +85,11 @@ PBIASLITEVMODE0 * 1 :SHL: 0
; RISC OS device numbers for each controller's IRQ line
MMC1_IRQ * OMAP44XX_IRQ_MMC1
MMC2_IRQ * OMAP44XX_IRQ_MMC2
MMC3_IRQ * OMAP44XX_IRQ_MMC3
MMC4_IRQ * OMAP44XX_IRQ_MMC4
MMC5_IRQ * OMAP44XX_IRQ_MMC5
MMC1_IRQ * OMAP44XX_IRQ_MMC1
MMC2_IRQ * OMAP44XX_IRQ_MMC2
MMC3_IRQ * OMAP44XX_IRQ_MMC3
MMC4_IRQ * OMAP44XX_IRQ_MMC4
MMC5_IRQ * OMAP44XX_IRQ_MMC5
; GPIO pin assignments
GBLS PB_LED_D1
......@@ -187,7 +187,7 @@ myvalue SETS "$field"
myvalue SETS "$value"
]
ASSERT . - %A0 = HALDevice_$class$field
[ ?HALDevice_$class$field = 2
[ ?HALDevice_$class$field = 2
DCW $myvalue
ELIF ?HALDevice_$class$field = 4
DCD $myvalue
......
......@@ -53,9 +53,9 @@ USB2_PHY_Reset_delay * 10000 ; 10msec
GPIO_HUB_NRESET * 62
GPIO_HUB_POWER * 1
OHCI_IRQ * OMAP44XX_IRQ_OHCI
EHCI_IRQ * OMAP44XX_IRQ_EHCI
MUSB_IRQ * OMAP44XX_IRQ_HS_USB_MC_N
OHCI_IRQ * OMAP44XX_IRQ_HSUSB_OHCI
EHCI_IRQ * OMAP44XX_IRQ_HSUSB_EHCI
MUSB_IRQ * OMAP44XX_IRQ_HSUSB_OTG
USB_Init
Push "lr"
......
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