Commit ec096f9e authored by Robert Sprowson's avatar Robert Sprowson
Browse files

Refactor HAL_VideoIICOp to be ATPCS

No longer specified to return _kernel_oserror * implements GraphicsV 14.
Make use of IICStatus defines instead of local copies.
Rename HAL_Video_ to HAL_Video.
Compiles, but not tested.


Version 0.11. Tagged as 'OMAP4-0_11'
parent 752d8b83
/* (0.10)
/* (0.11)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.10
#define Module_MajorVersion_CMHG 0.11
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 04 Jul 2012
#define Module_MajorVersion "0.10"
#define Module_Version 10
#define Module_MajorVersion "0.11"
#define Module_Version 11
#define Module_MinorVersion ""
#define Module_Date "04 Jul 2012"
......@@ -18,6 +18,6 @@
#define Module_ComponentName "OMAP4"
#define Module_ComponentPath "castle/RiscOS/Sources/HAL/OMAP4"
#define Module_FullVersion "0.10"
#define Module_HelpVersion "0.10 (04 Jul 2012)"
#define Module_LibraryVersionInfo "0:10"
#define Module_FullVersion "0.11"
#define Module_HelpVersion "0.11 (04 Jul 2012)"
#define Module_LibraryVersionInfo "0:11"
......@@ -140,14 +140,6 @@ I2C_XCurrent # 4 ; Current iic_transfer ptr
I2C_XBytes # 4 ; Bytes transferred in stage so far
I2CBlockSize # 0
; HAL API I2C transfer states
ECOMPLETED * 0
EINPROGRESS * 1
ENOACK * 2
EBUSY * 3
EERROR * 5
] ; __HAL_I2C_HDR__
END
......@@ -13,8 +13,8 @@
; limitations under the License.
;
[ :LNOT: :DEF: __HAL_VIDEO_HDR__
GBLL __HAL_VIDEO_HDR__
[ :LNOT: :DEF: __HAL_VideoHDR__
GBLL __HAL_VideoHDR__
GET hdr.irqs44xx
......@@ -565,6 +565,6 @@ VideoDeviceDevice # HALDevice_VDU_Size
VideoWorkspace # 4 ; HAL workspace pointer
Video_DeviceSize * :INDEX: @
] ; __HAL_VIDEO_HDR__
] ; __HAL_VideoHDR__
END
......@@ -295,7 +295,7 @@ Audio_Init
LDR v1, OSentries+4*OS_IICOpV
BL TPSWrite
[ AudioDebug
CMP a1, #ECOMPLETED
CMP a1, #IICStatus_Completed
BEQ %FT10
DebugTX "Audio_Init: TWL6040_ACCCTL access failed!"
10
......@@ -310,7 +310,7 @@ Audio_Init
LDR v1, OSentries+4*OS_IICOpV
BL TPSRead
[ AudioDebug
CMP a1, #ECOMPLETED
CMP a1, #IICStatus_Completed
BEQ %FT20
DebugTX "Audio_Init: read of TWL6040 regs failed!"
20
......@@ -542,7 +542,7 @@ SetCodecMode
LDR v1, OSentries+4*OS_IICOpV
BL TPSWrite
[ AudioDebug
CMP a1, #ECOMPLETED
CMP a1, #IICStatus_Completed
EXIT EQ
DebugTX "SetCodecMode: TPS write failed!"
]
......@@ -649,7 +649,7 @@ PreDisable
BEQ %FT20
BL TPSWrite
[ AudioDebug
CMP a1, #ECOMPLETED
CMP a1, #IICStatus_Completed
BEQ %FT15
DebugReg a4,"PreDisable: Write failed, reg="
15
......@@ -1101,7 +1101,7 @@ UpdateHeadset
EXIT EQ
BL TPSWrite
[ AudioDebug
CMP a1, #ECOMPLETED
CMP a1, #IICStatus_Completed
BEQ %FT15
DebugReg a4,"UpdateHeadset: Write failed, reg="
15
......@@ -1194,7 +1194,7 @@ UpdateHandsFree
EXIT EQ
BL TPSWrite
[ AudioDebug
CMP a1, #ECOMPLETED
CMP a1, #IICStatus_Completed
BEQ %FT15
DebugReg a4,"UpdateHandsFree: Write failed, reg="
15
......
......@@ -221,21 +221,21 @@ HALdescriptor DATA
IMPORT HAL_NVMemoryWrite
IMPORT HAL_VideoFlybackDevice
IMPORT HAL_Video_SetMode
IMPORT HAL_Video_WritePaletteEntry
IMPORT HAL_Video_WritePaletteEntries
IMPORT HAL_Video_ReadPaletteEntry
IMPORT HAL_Video_SetInterlace
IMPORT HAL_Video_SetBlank
IMPORT HAL_Video_SetPowerSave
IMPORT HAL_Video_UpdatePointer
IMPORT HAL_Video_SetDAG
IMPORT HAL_Video_VetMode
IMPORT HAL_Video_PixelFormats
IMPORT HAL_Video_Features
IMPORT HAL_Video_BufferAlignment
IMPORT HAL_Video_OutputFormat
IMPORT HAL_Video_IICOp ; Implemented in s.I2C
IMPORT HAL_VideoSetMode
IMPORT HAL_VideoWritePaletteEntry
IMPORT HAL_VideoWritePaletteEntries
IMPORT HAL_VideoReadPaletteEntry
IMPORT HAL_VideoSetInterlace
IMPORT HAL_VideoSetBlank
IMPORT HAL_VideoSetPowerSave
IMPORT HAL_VideoUpdatePointer
IMPORT HAL_VideoSetDAG
IMPORT HAL_VideoVetMode
IMPORT HAL_VideoPixelFormats
IMPORT HAL_VideoFeatures
IMPORT HAL_VideoBufferAlignment
IMPORT HAL_VideoOutputFormat
IMPORT HAL_VideoIICOp ; Implemented in s.I2C
IMPORT HAL_UARTPorts
IMPORT HAL_UARTStartUp
......@@ -319,20 +319,20 @@ HAL_EntryTable DATA
HALEntry HAL_IICMonitorTransfer
HALEntry HAL_VideoFlybackDevice
HALEntry HAL_Video_SetMode
HALEntry HAL_Video_WritePaletteEntry
HALEntry HAL_Video_WritePaletteEntries
HALEntry HAL_Video_ReadPaletteEntry
HALEntry HAL_Video_SetInterlace
HALEntry HAL_Video_SetBlank
HALEntry HAL_Video_SetPowerSave
HALEntry HAL_Video_UpdatePointer
HALEntry HAL_Video_SetDAG
HALEntry HAL_Video_VetMode
HALEntry HAL_Video_PixelFormats
HALEntry HAL_Video_Features
HALEntry HAL_Video_BufferAlignment
HALEntry HAL_Video_OutputFormat
HALEntry HAL_VideoSetMode
HALEntry HAL_VideoWritePaletteEntry
HALEntry HAL_VideoWritePaletteEntries
HALEntry HAL_VideoReadPaletteEntry
HALEntry HAL_VideoSetInterlace
HALEntry HAL_VideoSetBlank
HALEntry HAL_VideoSetPowerSave
HALEntry HAL_VideoUpdatePointer
HALEntry HAL_VideoSetDAG
HALEntry HAL_VideoVetMode
HALEntry HAL_VideoPixelFormats
HALEntry HAL_VideoFeatures
HALEntry HAL_VideoBufferAlignment
HALEntry HAL_VideoOutputFormat
NullEntry ; HALEntry HAL_MatrixColumns
NullEntry ; HALEntry HAL_MatrixScan
......@@ -403,20 +403,20 @@ HAL_EntryTable DATA
NullEntry ;HALEntry HAL_MonitorLeadID
NullEntry ;HALEntry HAL_Video_Render
NullEntry ;HALEntry HAL_VideoRender
HALEntry HAL_USBPortPower
HALEntry HAL_USBPortStatus
HALEntry HAL_USBPortIRQ
HALEntry HAL_Video_IICOp
HALEntry HAL_VideoIICOp
NullEntry ; HAL_TimerIRQClear
NullEntry ; HAL_TimerIRQStatus
HALEntry HAL_ExtMachineID
NullEntry ; HAL_Video_FramestoreAddress
NullEntry ; HAL_VideoFramestoreAddress
HALEntry HAL_UARTDefault
......
......@@ -22,6 +22,8 @@
GET Hdr:OSEntries
GET Hdr:HALEntries
GET Hdr:FSNumbers
GET Hdr:NewErrors
GET hdr.omap4430
GET hdr.StaticWS
......@@ -37,7 +39,7 @@
EXPORT HAL_IICDevice
EXPORT HAL_IICTransfer
EXPORT HAL_IICMonitorTransfer
EXPORT HAL_Video_IICOp
EXPORT HAL_VideoIICOp
EXPORT IIC_DoOp_Poll
IMPORT HAL_CounterDelay
......@@ -52,7 +54,7 @@
; RISC OS sees it as I2C bus 1.
; I2C3 - routed to DVI-D connector (P1) and Camera Expansion connector (J17)
; This means its sole use is for reading EDID/DDC data.
; RISC OS therefore accesses it via HAL_Video_IICOp.
; RISC OS therefore accesses it via HAL_VideoIICOp.
; I2C4 - routed to WL1271 (BT/FM control) and Expansion Connectors J6 (future expansion)
; RISC OS does not use this bus at all, and neither does this code.
......@@ -243,7 +245,7 @@ HAL_IICDevice
; r1 = number of transfers
; r2 = iic_transfer array ptr
; out:
; r0 = E* return code
; r0 = IICStatus return code
; Transfer list format:
; typedef struct iic_transfer
; {
......@@ -261,7 +263,7 @@ HAL_IICDevice
HAL_IICTransfer
LDRB a4, [sb, #BoardConfig_NumI2C]
CMP a1, a4
MOVHS a1, #EERROR
MOVHS a1, #IICStatus_Error
MOVHS pc, lr
; Quickly validate the transfer list
; We have several constraints:
......@@ -271,11 +273,11 @@ HAL_IICTransfer
; there must be between 1 and 65536 bytes of data (but for the moment we do allow
; individual iic_transfers to be 0-length)
CMP a2, #0
MOVLT a1, #EERROR
MOVLT a1, #IICStatus_Error
MOVLT pc, lr
LDR a4, [a3]
TST a4, #1:SHL:31 ; First transfer has nostart set!
MOVNE a1, #EERROR
MOVNE a1, #IICStatus_Error
MOVNE pc, lr
STMFD sp!, {v1-v5,lr}
ADD a4, a3, a2, LSL #3
......@@ -292,11 +294,11 @@ HAL_IICTransfer
BNE %BT10 ; Still more data in this transfer
20
CMP v5, #65536
MOVHS a1, #EERROR ; Too much (or too little) data
MOVHS a1, #IICStatus_Error ; Too much (or too little) data
LDMHSIA sp! ,{v1-v5,pc}
CMP v1, a4
BNE %BT30
_IICTransfer_Video ; Entry point for HAL_Video_IICOp
_IICTransfer_Video ; Entry point for HAL_VideoIICOp
[ I2CDebug
DebugTX "HAL_IICTransfer"
DebugReg a1, "bus="
......@@ -313,7 +315,7 @@ _IICTransfer_Video ; Entry point for HAL_Video_IICOp
TEQ a4, #0 ; in use already?
STREQ a3, [v5, #I2C_XStart] ; if not, claim it
MSR CPSR_c, ip
MOVNE a1, #EBUSY ; if it is, return "BUSY"
MOVNE a1, #IICStatus_Busy ; if it is, return "BUSY"
[ I2CDebug
BEQ %FT10
DebugReg a4, "BUSY: XStart="
......@@ -380,7 +382,7 @@ start_transfer ; Start the transfer in v1
[ I2CDebug
DebugReg a4, "ISC_CON timeout: "
]
MOV a1, #EBUSY
MOV a1, #IICStatus_Busy
MOV v3, #0
STR v3, [v5, #I2C_XStart]
LDMFD sp!, {v1-v5,pc}
......@@ -448,7 +450,7 @@ start_transfer ; Start the transfer in v1
[ I2CDebug
DebugReg v3, "BB timeout: I2C_STAT="
]
MOV a1, #EBUSY
MOV a1, #IICStatus_Busy
B clear_and_return
20
; 6. configure I2C_CON.STT=1, I2C_CON.STP=0/1
......@@ -459,7 +461,7 @@ start_transfer ; Start the transfer in v1
[ I2CDebug
DebugTX "Transfer started"
]
MOV a1, #EINPROGRESS
MOV a1, #IICStatus_InProgress
LDMFD sp!, {v1-v5,pc}
; For receive:
......@@ -470,7 +472,7 @@ start_transfer ; Start the transfer in v1
; 1. Use I2C_IE.XRDY_IE
; 2. Except we use I2C_IE.XDR_IE if the length doesn't match the TX FIFO threshold?
; Return E* state for transfer on bus r0
; Return IICStatus state for transfer on bus r0
; Called on appropriate interrupt
HAL_IICMonitorTransfer
; Process the interrupts, according to figures 18-31/18-32 in spruf98b
......@@ -488,7 +490,7 @@ HAL_IICMonitorTransfer
]
LDRH v3, [v4, #I2C_STAT]
TEQ a1, #0 ; If no transfer, shut off all interrupts
ASSERT ECOMPLETED=0
ASSERT IICStatus_Completed=0
[ I2CDebug
BNE %FT10
DebugTX "No XStart!"
......@@ -522,14 +524,14 @@ HAL_IICMonitorTransfer
; Clear XUDF, ROVR, BB, BF - they're status bits and don't indicate anything
; we care about here
CMP v3, #0
MOVEQ a1, #EINPROGRESS ; If nothing interesting happened, claim everything is OK (required for polling-mode transfers, e.g. HAL_Video_IICOp)
MOVEQ a1, #IICStatus_InProgress ; If nothing interesting happened, claim everything is OK (required for polling-mode transfers, e.g. HAL_VideoIICOp)
LDMEQFD sp!, {v1-v5,pc}
; Else bad stuff - unhandled interrupt
[ I2CDebugError
DebugReg v3, "Unhandled IRQ - "
]
unexpected_error
MOV a1, #EERROR
MOV a1, #IICStatus_Error
; recover from error situation
recover_from_error
MOV v2, #0
......@@ -545,7 +547,7 @@ clear_and_return
[ I2CDebug
DebugReg a1, "clear_and_return: "
]
CMP a1, #EINPROGRESS
CMP a1, #IICStatus_InProgress
BHI recover_from_error
STRH v3, [v4, #I2C_STAT]
MOV v3, #0
......@@ -555,7 +557,7 @@ clear_and_return
i2c_nack
; No ack was received - give up and return error
MOV a1, #ENOACK
MOV a1, #IICStatus_NoACK
B clear_and_return
i2c_al
......@@ -582,7 +584,7 @@ i2c_ardy
]
LDR a4, [v5, #I2C_XEnd]
CMP a3, a4
MOVEQ a1, #ECOMPLETED
MOVEQ a1, #IICStatus_Completed
BEQ clear_and_return
; Skip any zero-length nostart transfers that follow this one
ADD v1, a3, #12
......@@ -601,7 +603,7 @@ i2c_ardy
BNE unexpected_error ; nostart transfer with nonzero length = hardware hasn't requested full number of bytes
]
CMP v1, a4
MOVEQ a1, #ECOMPLETED
MOVEQ a1, #IICStatus_Completed
BEQ clear_and_return
ADD v1, v1, #12
B %BT10
......@@ -649,7 +651,7 @@ send_bytes
DebugTX ""
]
STR a3, [v5, #I2C_XBytes]
MOV a1, #EINPROGRESS
MOV a1, #IICStatus_InProgress
STRH v3, [v4, #I2C_STAT]
LDMIA sp!, {v1-v5,pc}
20
......@@ -725,7 +727,7 @@ read_bytes
STR a2, [v2, #4] ; Update checksum
STR a3, [v5, #I2C_XBytes]
15
MOV a1, #EINPROGRESS
MOV a1, #IICStatus_InProgress
STRH v3, [v4, #I2C_STAT]
LDMIA sp!, {v1-v5,pc}
20
......@@ -759,79 +761,97 @@ read_bytes
B %BT10
; HAL_Video_IICOp
; Officially:
; r0 = card<<28 + channel<<24 + I2Ccmnd << 16 + address
; I2Ccmnd = 1 for read, 0 write
; r1 = DMA address
; r2 = byte count
; Returns:
; r0 = 0 or error block
; r1 updated
; r2 updated
; In reality:
; r0 = as above. The NVidia driver describes 'address' as being 11-bit, but only seems to handle it as 8-bit. The address is the offset to read from in the EDID data (Only EDID is supported, at I2C address 0x50. DDC, which is apparently at 0x37, isn't supported)
; r1 = logical address
; r2 = byte count
; Returns:
; r0 = 0 on success, unmodified on error (which also be 0 for a write to 0 on card 0 channel 0?!)
; r1 = r1+r2 on success, unmodified on error
; r2 = 0 on success, unmodified on error
; There appears to be no support for partial transfers; NVidia driver implementation simply writes corrupt data for any failed bytes.
HAL_Video_IICOp
; int HAL_VideoIICOp(uint32_t op, uint8_t *buffer, uint32_t *size)
; in:
; r0 = b0-15 offset within IIC device to start at (currently assumed 8 bit)
; b16-23 base IICAddress
; b24-31 zero
; r1 = buffer to read from/write to
; r2 = pointer to number of bytes to transfer
; returns:
; r0 = IICStatus return code
; size = bytes successfully transferred (prior to any error)
HAL_VideoIICOp
; Make sure we've got a valid IIC bus to use
LDRB a4, [sb, #BoardConfig_VideoI2C]
CMP a4, #255
MOV ip, #0
STREQ ip, [a3]
MOVEQ a1, #IICStatus_Error
MOVEQ pc, lr
; Check for input passed end
UBFX a4, a1, #0, #16
CMP a4, #256
STRCS ip, [a3]
MOVCS a1, #IICStatus_Completed
MOVCS pc, lr
; Clip request at end
Push "a1-a3,lr"
LDR a3, [a3]
ADD ip, a4, a3
CMP ip, #256
RSBHI a3, a4, #256
; Build a set of iic_transfer blocks and call RISCOS_IICOpV
; First let's discard writes, to be equivalent to the NVidia driver
TST a1, #1<<16
; Also make sure we've got a valid IIC bus to use
LDRB a4, [sb, #BoardConfig_VideoI2C]
CMPNE a4, #255
MOVEQ pc, lr
; Also check we're transferring a valid number of bytes
SUB a4, a3, #1
CMP a4, #65536
MOVHS pc, lr
Push "a1-a3,lr"
; Now we construct two iic_transfer blocks
; - First block is a write to 0x50. Single byte containing EDID start address (lower 8 bits of r0)
; - Second block is a read from 0x50. r2 bytes written to r1.
; We construct two iic_transfer blocks
; - First block is a single byte write containing the start address (lower 8 bits of r0)
; - Second block is a read. r2 bytes written to r1.
; Block 2:
TST a1, #1<<16 ; Is this read or write? (although this code isn't guaranteed to work properly for EDID writes!)
MOVNE a1, #&a1 ; Read from I2C
MOVEQ a1, #&a0 ; Write to I2C
Push "a1-a3" ; Push the block on the stack (a2 & a3 are already correct)
UBFX a1, a1, #16, #8 ; Extract base IICAddress
Push "a1-a3" ; Push the block on the stack (a2 & a3 are already correct)
; Block 1:
MOV a1, #&a0
ADD a2, sp, #12 ; sp+12 should point to the 8 bit EDID address
MOV a3, #1
Push "a1-a3"
BIC a1, a1, #1 ; Clear RnW of base address
ADD a2, sp, #12 ; sp+12 should point to the 8 bit offset
MOV a3, #1
Push "a1-a3"
; Now attempt to start the transfer
LDRB a2, [sb, #BoardConfig_VideoI2C]
MOV a2, a2, LSL #24
ADD a2, a2, #2
MOV a1, sp
; If HAL_Init isn't done yet, we can't use OS_IICOpV
LDR a3, HALInitialised
CMP a3, #0
ADREQ a3, IIC_DoOp_Poll
LDRNE a3, OSentries+4*OS_IICOpV
BLX a3
; On error, return with unmodified regs, ala NVidia driver
CMP a1, #0
ADD sp, sp, #24
Pull "a1-a3,lr"
ADDEQ a2, a2, a3
MOVEQ a1, #0
MOVEQ a3, #0
MOV pc, lr
LDRB a2, [sb, #BoardConfig_VideoI2C]
MOV a2, a2, LSL #24
ADD a2, a2, #2
MOV a1, sp
; If HAL_Init isn't done yet, we can't use RISCOS_IICOpV
LDR a3, HALInitialised
CMP a3, #0
BEQ %FT10
LDR a3, OSentries+4*OS_IICOpV
BLX a3
; Unmap RISC OS error numbers to IICStatus return codes
ASSERT IICStatus_Completed = 0
TEQ a1, #0
LDRNE a1, [a1]
LDRNE lr, =ErrorNumber_IIC_NoAcknowledge
SUBNE a1, a1, lr ; 0/1/2 = NoAck/Error/Busy
USAT a1, #2, a1 ; 4+ => 3 = Error
ADRNE lr, %FT05
LDRNEB a1, [lr, a1]
B %FT20
05
ASSERT (ErrorNumber_IIC_Error - ErrorNumber_IIC_NoAcknowledge) = 1
ASSERT (ErrorNumber_IIC_Busy - ErrorNumber_IIC_NoAcknowledge) = 2
DCB IICStatus_NoACK, IICStatus_Error, IICStatus_Busy, IICStatus_Error
10
BL IIC_DoOp_Poll
20
; In case of error, assume nothing got transferred at all
CMP a1, #IICStatus_Completed
LDREQ a4, [sp, #(3*4)+(2*4)] ; Clipped block 2 request size
MOVNE a4, #0
ADD sp, sp, #24 ; Junk the iic_transfer blocks
STR a1, [sp, #0] ; Propagate return code
LDR a3, [sp, #8]
STR a4, [a3] ; Actual transfer size
Pull "a1-a3,pc"
IIC_DoOp_Poll
; IIC transfer function that performs a polling transfer, similar to HAL_Video_IICOp
; IIC transfer function that performs a polling transfer, similar to HAL_VideoIICOp
; This allows us to do IIC transfers before RISC OS is fully initialised (e.g. from inside HAL_Init)
; Parameters are identical to RISCOS_IICOpV:
; r0 = iic_transfer array ptr
; r1 = bits 0-23: iic_transfer count
; bits 24-31: bus number
; Returns E* return code in R0 (0 success, anything else failure)
; Returns IICStatus return code in R0 (0 success, anything else failure)
Push "v1,lr"
[ {FALSE}
; If IRQs and IIC IRQ are enabled, panic
......@@ -857,7 +877,7 @@ IIC_DoOp_Poll
BL HAL_IICTransfer
; Now just poll until we're done
10
CMP a1, #EINPROGRESS ; Done?
CMP a1, #IICStatus_InProgress ; Done?
Pull "v1,pc", NE
ADR lr, %BT10
MOV a1, v1
......
......@@ -151,7 +151,7 @@ RTCReadTime
MOV a4, #RTC_STATUS_REG
MOV a2, sp
BL TPSRead
CMP a1, #ECOMPLETED
CMP a1, #IICStatus_Completed
LDRB ip, [a2]
MOV a1, #RTCRetCode_InvalidTime
MOVNE a1, #RTCRetCode_Error
......@@ -164,7 +164,7 @@ RTCReadTime
MOV a1, #TPSRTC_IIC*2
MOV a4, #RTC_CTRL_REG
BL TPSWrite
CMP a1, #ECOMPLETED
CMP a1, #IICStatus_Completed
MOVNE a1, #RTCRetCode_Error
ADD sp, sp, #4
Pull "v1-v3,pc", NE
......@@ -179,10 +179,10 @@ RTCReadTime
MOV a3, #6
MOV a4, #SECONDS_REG
BL TPSRead
CMP a1, #ECOMPLETED
CMP a1, #IICStatus_Completed
MOVNE a1, #RTCRetCode_Error
Pull "v1-v3,pc", NE
ASSERT ECOMPLETED = 0
ASSERT IICStatus_Completed = 0
STRB a1, [v3, #RTCTimeStruct_BCD_Centiseconds] ; No centisecond time
; Construct a fakey YearHI by looking at YearLO
; Anything 70 or above is considered 1970+, else 2000+
......@@ -220,7 +220,7 @@ RTCWriteTime
MOV a4, #RTC_CTRL_REG
MOV a2, sp
BL TPSWrite
CMP a1, #ECOMPLETED
CMP a1, #IICStatus_Completed
MOVNE a1, #RTCRetCode_Error
ADDNE sp, sp, #4
Pull "v1-v3,pc", NE
......@@ -246,7 +246,7 @@ RTCWriteTime
SUBEQS a3, a3, #3
BEQ %FT01 ; Nothing left to write!
BL TPSWrite
CMP a1, #ECOMPLETED
CMP a1, #IICStatus_Completed
MOVNE a1, #RTCRetCode_Error
ADDNE sp, sp, #4
Pull "v1-v3,pc", NE
......@@ -257,8 +257,8 @@ RTCWriteTime
MOV a4, #RTC_CTRL_REG
MOV a1, #TPSRTC_IIC*2
BL TPSWrite
CMP a1, #ECOMPLETED
ASSERT RTCRetCode_OK = ECOMPLETED
CMP a1, #IICStatus_Completed
ASSERT RTCRetCode_OK = IICStatus_Completed
MOVNE a1, #RTCRetCode_Error
ADD sp, sp, #4
Pull "v1-v3,pc"
......
......@@ -35,20 +35,20 @@
EXPORT Video_init
EXPORT HAL_VideoFlybackDevice
EXPORT HAL_Video_SetMode
EXPORT HAL_Video_WritePaletteEntry
EXPORT HAL_Video_WritePaletteEntries
EXPORT HAL_Video_ReadPaletteEntry
EXPORT HAL_Video_SetInterlace
EXPORT HAL_Video_SetBlank
EXPORT HAL_Video_SetPowerSave
EXPORT HAL_Video_UpdatePointer
EXPORT HAL_Video_SetDAG
EXPORT HAL_Video_VetMode
EXPORT HAL_Video_PixelFormats
EXPORT HAL_Video_Features
EXPORT HAL_Video_BufferAlignment
EXPORT HAL_Video_OutputFormat
EXPORT HAL_VideoSetMode
EXPORT HAL_VideoWritePaletteEntry
EXPORT HAL_VideoWritePaletteEntries
EXPORT HAL_VideoReadPaletteEntry