Commit cf16b564 authored by Robert Sprowson's avatar Robert Sprowson
Browse files

Add support for all 4 I2C interfaces hdr.board support all 4 I2C interfaces...

Add support for all 4 I2C interfaces hdr.board support all 4 I2C interfaces added BoardFlags variable remove unused BoardConfig_APLL_CTL variable hdr.StaticWS support all 4 I2C interfaces on OMAP4 board.s removed unused parameter apll_ctl added support for all 4 I2C and UART interfaces added BoardFlags variable

Boot.s
    support all 4 I2C interfaces
    some code tweaks (tidy up)
    removed unused Touchbook code
I2C.s
    support all 4 I2C interfaces
    some code cleanup and comment correction
Submission from Willi Theiss.

Version 0.19. Tagged as 'OMAP4-0_19'
parent 8a75792e
/* (0.18)
/* (0.19)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.18
#define Module_MajorVersion_CMHG 0.19
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 17 Aug 2013
#define Module_Date_CMHG 01 Sep 2013
#define Module_MajorVersion "0.18"
#define Module_Version 18
#define Module_MajorVersion "0.19"
#define Module_Version 19
#define Module_MinorVersion ""
#define Module_Date "17 Aug 2013"
#define Module_Date "01 Sep 2013"
#define Module_ApplicationDate "17-Aug-13"
#define Module_ApplicationDate "01-Sep-13"
#define Module_ComponentName "OMAP4"
#define Module_ComponentPath "castle/RiscOS/Sources/HAL/OMAP4"
#define Module_FullVersion "0.18"
#define Module_HelpVersion "0.18 (17 Aug 2013)"
#define Module_LibraryVersionInfo "0:18"
#define Module_FullVersion "0.19"
#define Module_HelpVersion "0.19 (01 Sep 2013)"
#define Module_LibraryVersionInfo "0:19"
......@@ -73,10 +73,8 @@ L4_GPIO4_Log # 4 ; L4_GPIO4 base address
L4_GPIO5_Log # 4 ; L4_GPIO5 base address
L4_GPIO6_Log # 4 ; L4_GPIO6 base address
I2C_Table # 0 ; Table of I2C HW ptrs & transfer states
I2C1Block # I2CBlockSize
I2C2Block # I2CBlockSize
I2C3Block # I2CBlockSize
MaxI2CControllers * 4
I2C_Table # (MaxI2CControllers*I2CBlockSize) ; I2C HW ptrs & transfer states
[ DebugInterrupts
LastInterrupt_IRQ # 4 ; Last IRQ, -1 if cleared
......
......@@ -24,14 +24,14 @@ BoardConfig_DebugUART # 4 ; Physical address of debug UART
BoardConfig_HALUART # 4*4 ; Physical addresses of UARTs, in HAL API order
BoardConfig_HALUARTIRQ # 4 ; 4 bytes of IRQ numbers for HAL UARTs
BoardConfig_DefaultUART # 1 ; Default UART index
# 3 ; Spare
BoardConfig_BoardFlags # 1 ; flags used for PlatformInfo
# 2 ; Spare
BoardConfig_HALI2C # 4*3 ; Physical addresses of I2Cs, in HAL API order
BoardConfig_HALI2CIRQ # 3 ; 3 bytes of IRQ numbers of HAL I2Cs
BoardConfig_NumI2C # 1 ; Number of I2Cs to expose via HAL
BoardConfig_HALI2C # 4*4 ; Physical addresses of I2Cs, in HAL API order
BoardConfig_HALI2CIRQ # 4 ; 4 bytes of IRQ numbers of HAL I2Cs
BoardConfig_NumI2C # 1 ; Number of I2Cs to expose via HAL
BoardConfig_VideoI2C # 1 ; Index of video I2C bus in above tables, 255 for none
BoardConfig_APLL_CTL # 1 ; APLL_CTL value for TPS audio
BoardConfig_VideoGPIO # 1 ; GPIOx of DVI framer, 255 for none
BoardConfig_USBGPIO # 1 ; GPIOx of USB PHY, 255 for none
......
......@@ -58,9 +58,6 @@ MoreDebug SETL Debug :LAND: {FALSE}
IMPORT DebugHALPrintByte
IMPORT RTC_Init
IMPORT DebugCallstack
IMPORT TPSRead
IMPORT TPSWrite
IMPORT IIC_DoOp_Poll
; v8 is used as pointer to RISC OS entry table throughout pre-MMU stage.
MACRO
......@@ -558,15 +555,19 @@ HAL_Init
10 BL phys2log
SUBS a1, a1, #4
BGE %BT10
; handle supported I2C interfaces (at most MaxI2CControllers)
LDRB v1, [sb, #BoardConfig_NumI2C]
CMP v1, #MaxI2CControllers
MOVGT v1, #MaxI2CControllers
ADR v2, (I2C_Table + I2C_HW)
MOV a1, #BoardConfig_HALI2C
10
BL phys2log
STR a2, (I2C1Block + I2C_HW)
MOV a1, #(BoardConfig_HALI2C + 4)
BL phys2log
STR a2, (I2C2Block + I2C_HW)
MOV a1, #(BoardConfig_HALI2C + 8)
BL phys2log
STR a2, (I2C3Block + I2C_HW)
STR a2, [v2], #I2CBlockSize
ADD a1, a1, #4
SUBS v1, v1, #1
BGT %BT10
[ Debug
DebugTX "HAL_Init"
......@@ -775,12 +776,7 @@ HAL_HardwareInfo
MOV pc, lr
HAL_PlatformInfo
; TouchBook can do soft-off, others can't (yet)
LDR ip, [sb, #BoardConfig_MachID]
LDR a1, =MachID_TouchBook
CMP ip, a1
MOVNE ip, #2_10000 ; no podules,no PCI cards,no multi CPU,no soft off,and soft ROM
MOVEQ ip, #2_11000
LDRB ip, [sb, #BoardConfig_BoardFlags]
STR ip, [a2]
MOV ip, #2_11111 ; mask of valid bits
STR ip, [a3]
......@@ -875,23 +871,12 @@ HAL_PhysTable
DCD 0
HAL_Reset
; TouchBook can power off by setting GPIO168 to 0
; TODO - Sort out the other machine types
LDR a3, [sb, #BoardConfig_MachID]
LDR a2, =MachID_TouchBook
CMP a3, a2
CMPEQ a1, #0
; Reset or power off?
CMP a1, #0
BNE %FT10
MOV a1, #168
MOV a2, #0
BL GPIOx_SetAsOutput
; It seems like there's a short delay before the system shuts down; if we try doing a
; soft reset during that time then we'll hang with the power still on
; So just loop here, with a warning message for if something's gone wrong
DebugTX "TouchBook power off failed!"
B .
10
; At the moment we only support resets, not power off
; Reset, or power off not supported
; For a reset, we just poke PRM_RSTCTRL.RST_GLOBAL_WARM_software
LDR a3, L4_PowerMan_Log
ADD a3, a3, #DEVICE_PRM
......
......@@ -44,7 +44,7 @@
IMPORT HAL_CounterDelay
; The OMAP4430 has 4 I2C controllers:
; The OMAP4430 has 5 I2C controllers:
; (usage on pandaboard)
; I2C1 - connected to the TWL6030 (power) and TWL6040 (audio) companion chip
; RISC OS sees it as I2C bus 0.
......@@ -56,7 +56,9 @@
; This means its sole use is for reading EDID/DDC data.
; RISC OS therefore accesses it via HAL_VideoIICOp.
; I2C4 - routed to WL1271 (BT/FM control) and Expansion Connectors J6 (future expansion)
; RISC OS does not use this bus at all, and neither does this code.
; RISC OS sees it as I2C bus 3.
; I2C5 - used for SmartReflex control (part of PRCM) in connection with TWL6030 power chip
; RISC OS does not see this bus at all.
GBLL I2CDebug
I2CDebug SETL {FALSE} :LAND: Debug
......@@ -88,22 +90,12 @@ I2C_Init
DebugTX "I2C_Init"
]
; clocks are already activated by u-boot
; ; 1. Make sure clocks are enabled
; LDR a1, L4_ClockMan_Log
; LDR a2, [a1, #CM_ICLKEN1_CORE]
; ORR a2, a2, #7:SHL:15
; STR a2, [a1, #CM_ICLKEN1_CORE]
; LDR a2, [a1, #CM_FCLKEN1_CORE]
; ORR a2, a2, #7:SHL:15
; STR a2, [a1, #CM_FCLKEN1_CORE]
; ; Wait for power?
; MOV a1, #50*1024 ; 50msec ish
; BL HAL_CounterDelay
; clocks are already activated by u-boot
; 2. Initialise each I2C controller
MOV v1, #3
MOV v1, #MaxI2CControllers ; max # of supported I2C interfaces
ADR v2, I2C_Table
10
[ I2CDebug
......@@ -118,18 +110,11 @@ I2C_Init
BEQ %FT20
MOV a4, #0
STRH a4, [v3, #I2C_CON]
; The manual makes no mention of it, but u-boot waits for a while after
; enabling & disabling each controller. So to play it safe I'll follow u-boot's lead.
; MOV a1, #50*1024 ; 50msec ish
; BL HAL_CounterDelay
20
MOV a4, #I2C_SYSC_SRST ; soft reset
STRH a4, [v3, #I2C_SYSC]
MOV a4, #I2C_CON_EN
STRH a4, [v3, #I2C_CON]
; ; Wait
; MOV a1, #10*1024 ; 10msec ish
; BL HAL_CounterDelay
20
LDRH a4, [v3, #I2C_SYSS]
TST a4, #I2C_SYSS_RDONE ; reset done
......@@ -137,21 +122,26 @@ I2C_Init
; Now disable the controller again so we can program it properly
MOV a4, #0
STRH a4, [v3, #I2C_CON]
; ; Wait
; MOV a1, #50*1024 ; 50msec ish
; BL HAL_CounterDelay
; setup clock values according Table 23-9 (OMAP4 TRM Rev. O)
; setup clock values according Table 23-8 and 23-9 (OMAP4 TRM Rev. O)
; based on I2Cn_FCLK 96 MHz
; PSC SCLL SCLH
; 100 kHz: 23 13 15
; 400 kHz: 9 5 7
;
; fInternal = I2Cn_FCLK / (PSC + 1)
; tLow = (SCLL + 7) * 1 / fInternal
; tHigh = (SCLH + 5) * 1 / fInternal
; fI2Cn = 1 / (tLow + tHigh)
; tLow == tHigh ==> valSCL = fInternal / (2 * fI2Cn)
;
; PSC SCLL SCLH fInternal valSCL
; 100 kHz: 23 13 15 4.0 MHz 20
; 400 kHz: 9 5 7 9.6 MHz 12
;
; Run at 400kbps for now. TODO - Add support for higher speeds!
MOV a4, #(10 - 1) ; 9.6 MHz
STRH a4, [v3, #I2C_PSC]
MOV a4, #(6 - 1)
MOV a4, #(12 - 7)
STRH a4, [v3, #I2C_SCLL]
MOV a4, #(8 - 1)
MOV a4, #(12 - 5)
STRH a4, [v3, #I2C_SCLH]
; Program own address
MOV a4, #1
......@@ -176,9 +166,6 @@ I2C_Init
SUBS v1, v1, #1
ADD v2, v2, #I2CBlockSize
BNE %BT10
; ; Wait for last controller to init fully
; MOV a1, #10*1024 ; 10msec ish
; BL HAL_CounterDelay
; Done
30
[ I2CDebug
......@@ -497,8 +484,7 @@ HAL_IICMonitorTransfer
TEQ a1, #0 ; reset EQ condition
10
]
; STREQH a1, [v4, #I2C_IE]
MOV a1,#-1
MOVEQ a1,#-1
STREQH a1, [v4, #I2C_IRQENABLE_CLR]
STREQH v3, [v4, #I2C_STAT]
LDMEQFD sp!, {v1-v5,pc}
......@@ -538,6 +524,7 @@ recover_from_error
STRH v2, [v4, #I2C_CON]
MOV v3, #-1
STRH v3, [v4, #I2C_STAT]
STRH v3, [v4, #I2C_IRQENABLE_CLR]
STR v2, [v5, #I2C_XStart]
STRH v2, [v4, #I2C_CNT]
MOV v2, #I2C_CON_EN
......@@ -550,6 +537,8 @@ clear_and_return
CMP a1, #IICStatus_InProgress
BHI recover_from_error
STRH v3, [v4, #I2C_STAT]
MOV v3, #-1
STRH v3, [v4, #I2C_IRQENABLE_CLR]
MOV v3, #0
STR v3, [v5, #I2C_XStart]
STRH v3, [v4, #I2C_CNT]
......@@ -613,7 +602,7 @@ i2c_xdr
[ I2C_USE_FIFO
; Transfer I2C_BUFSTAT[5:0] bytes
LDRH a4, [v4, #I2C_BUFSTAT]
AND a4, a4, #&3F
AND a4, a4, #I2C_BUFSTAT_TXSTAT
|
MOV a4, #1
] ; I2C_USE_FIFO
......@@ -623,7 +612,7 @@ i2c_xrdy
[ I2C_USE_FIFO
; Transfer I2C_BUF[5:0]+1 bytes
LDRH a4, [v4, #I2C_BUF]
AND a4, a4, #&3F
AND a4, a4, #I2C_BUF_TXTRSH
ADD a4, a4, #1
|
MOV a4, #1
......@@ -682,8 +671,8 @@ i2c_rdr
[ I2C_USE_FIFO
; Read I2C_BUFSTAT[13:8] bytes
LDRH a4, [v4, #I2C_BUFSTAT]
MOV a4, a4, LSR #8
ANDS a4, a4, #&3F ; ERRATA - sometimes RDR is set when there's no data. So, don't attempt to read from the empty buffer.
ANDS a4, a4, #I2C_BUFSTAT_RXSTAT ; ERRATA - sometimes RDR is set when there's no data. So, don't attempt to read from the empty buffer.
MOVNE a4, a4, LSR #I2C_BUFSTAT_RXSTAT_SHIFT
BEQ %FT15
|
MOV a4, #1
......@@ -694,8 +683,8 @@ i2c_rrdy
[ I2C_USE_FIFO
; Read I2C_BUF[13:8]+1 bytes
LDRH a4, [v4, #I2C_BUF]
MOV a4, a4, LSR #8
AND a4, a4, #&3F
AND a4, a4, #I2C_BUF_RXTRSH
MOV a4, a4, LSR #I2C_BUF_RXTRSH_SHIFT
ADD a4, a4, #1
|
MOV a4, #1
......
......@@ -21,7 +21,7 @@
[ "$string" = ""
% $len*4
|
string2 SETS " DCD $pre" :CC: ("$string" :LEFT: 1) :CC: "$post"
string2 SETS " DCD $pre" :CC: ("$string" :LEFT: 1) :CC: "$post"
$string2
string2 SETS " DCDArray " :CC: ("$string" :RIGHT: ((:LEN: "$string")-1)) :CC: "," :CC: :STR: ($len-1) :CC: ",$pre,$post"
$string2
......@@ -38,7 +38,7 @@ string2 SETS " DCDArray " :CC: ("$string" :RIGHT: ((:LEN: "$string")-1)) :CC:
[ "$string" = ""
% $len
|
string2 SETS " DCB $pre" :CC: ("$string" :LEFT: 1) :CC: "$post"
string2 SETS " DCB $pre" :CC: ("$string" :LEFT: 1) :CC: "$post"
$string2
string2 SETS " DCBArray " :CC: ("$string" :RIGHT: ((:LEN: "$string")-1)) :CC: "," :CC: :STR: ($len-1) :CC: ",$pre,$post"
$string2
......@@ -51,20 +51,20 @@ string2 SETS " DCBArray " :CC: ("$string" :RIGHT: ((:LEN: "$string")-1)) :CC:
; Big ugly macro for defining a board config
; Note - $mixers is the set of enabled mixers (not including the system)
MACRO
BOARDCFG $name, $debuguart, $haluarts, $defaultuart, $hali2cs, $numi2c, $videoi2c, $apll_ctl, $videogpio, $usbgpio, $machid, $mixers, $vbcflags, $vbclcdnum, $vbclcdptr, $haldevices
BOARDCFG $name, $debuguart, $haluarts, $defaultuart, $hali2cs, $numi2c, $videoi2c, $videogpio, $usbgpio, $machid, $mixers, $vbcflags, $vbclcdnum, $vbclcdptr, $haldevices
01
DCD $debuguart
DCDArray "$haluarts", 4, L4_UART
DCBArray "$haluarts", 4, UART, _IRQ
DCB $defaultuart-1
% 3
DCB 2_10100 ; BoardFlags: no podules,no PCI cards,multi CPU,no soft off,and soft ROM
% 2
ASSERT (:LEN: "$hali2cs") >= $numi2c
ASSERT ((:LEN: "$hali2cs") >= $videoi2c) :LOR: ($videoi2c = 255)
DCDArray "$hali2cs", 3, L4_I2C
DCBArray "$hali2cs", 3, I2C, _IRQ
DCDArray "$hali2cs", 4, L4_I2C
DCBArray "$hali2cs", 4, I2C, _IRQ
DCB $numi2c
DCB $videoi2c
DCB $apll_ctl
DCB $videogpio
DCB $usbgpio
ASSERT MixerChannels = 8
......@@ -126,9 +126,9 @@ VBC_C * VideoBoardConfig_Flags_Composite
; And now the table of board configs
BoardConfigTable
; Name DebugUART UARTs DefaultUART I2Cs NumI2C VideoI2C APLL_CTL VideoGPIO USBGPIO MachID MixerChans VBC_Flags VBC_LCDNum VBC_LCDPtr InitDevices
BOARDCFG "PandaBoard", L4_UART3, "123", 3, "123", 3, 2, &16, 0, 1, MachID_PandaBoard, M_HSO+M_AI, VBC_C, 1, VBC_DVI, Panda
BOARDCFG "SDP4430", L4_UART3, "123", 3, "123", 3, 2, &16, 170, 24, MachID_OMAP4430SDP, M_HSO+M_AI, 0, 1, VBC_DVI, None
; Name DebugUART UARTs DefaultUART I2Cs NumI2C VideoI2C VideoGPIO USBGPIO MachID MixerChans VBC_Flags VBC_LCDNum VBC_LCDPtr InitDevices
BOARDCFG "PandaBoard", L4_UART3, "1234", 3, "1234", 4, 2, 0, 1, MachID_PandaBoard, M_HSO+M_AI, VBC_C, 1, VBC_DVI, Panda
BOARDCFG "SDP4430", L4_UART3, "1234", 3, "1234", 4, 2, 170, 24, MachID_OMAP4430SDP, M_HSO+M_AI, 0, 1, VBC_DVI, None
BoardConfigTable_End
; DSI_BPP DSI_LANES ACBias_freq LCDType Flags LCDTimings Max_PixelRate
......
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