Rework of detection of active interrupt source

Avoids stalling of the interrupt system in some circumstances, in particular when shutting down the computer.
Submission from Willi Theiss.
Built, but not tested here.

Version 0.31. Tagged as 'OMAP4-0_31'

VersionNum

-/* (0.30)
+/* (0.31)
  *
  * This file is automatically maintained by srccommit, do not edit manually.
  * Last processed by srccommit version: 1.1.
  *
  */
-#define Module_MajorVersion_CMHG        0.30
+#define Module_MajorVersion_CMHG        0.31
 #define Module_MinorVersion_CMHG        
 #define Module_Date_CMHG                22 Mar 2014
 
-#define Module_MajorVersion             "0.30"
-#define Module_Version                  30
+#define Module_MajorVersion             "0.31"
+#define Module_Version                  31
 #define Module_MinorVersion             ""
 #define Module_Date                     "22 Mar 2014"
 
@@ -18,6 +18,6 @@
 #define Module_ComponentName            "OMAP4"
 #define Module_ComponentPath            "castle/RiscOS/Sources/HAL/OMAP4"
 
-#define Module_FullVersion              "0.30"
-#define Module_HelpVersion              "0.30 (22 Mar 2014)"
-#define Module_LibraryVersionInfo       "0:30"
+#define Module_FullVersion              "0.31"
+#define Module_HelpVersion              "0.31 (22 Mar 2014)"
+#define Module_LibraryVersionInfo       "0:31"

s/Interrupts

@@ -162,25 +162,17 @@ HAL_IRQDisable
         MRS     a4, CPSR
         ORR     a3, a4, #F32_bit+I32_bit
         MSR     CPSR_c, a3
-        ; Check if this is actually an IRQ
-        LDR     a3, MPU_INTC_Log
-;       ASSERT  INTCPS_ILR_SIZE = 4
-;       ADD     a2, a3, a1, LSL #2
-;       LDR     a2, [a2, #INTCPS_ILR]
-;       TST     a2, #1
-;       MOVNE   a1, #0 ; This is an FIQ, so don't disable it
-;       MSRNE   CPSR_c, a4
-;       Pull    "pc", NE
         ; Now mask the interrupt
+        LDR     a3, MPU_INTC_Log
         ADD     ip, a3, #(MPU_INTC_DIST + GIC_DIST_ENABLE_CLEAR)
         AND     a2, a1, #31     ; bit   = intno % 32
         MOV     lr, a1, LSR #5  ; index = intno / 32
         ADD     ip, ip, lr, LSL #2
         MOV     lr, #1
         MOV     a2, lr, LSL a2  ; mask = (1 << bit)
-        SUB     lr, ip, #(GIC_DIST_ENABLE_CLEAR - GIC_DIST_ENABLE_SET)
-        LDR     lr, [lr, #0]    ; get old state (from ENABLE_SET reg)
+        LDR     lr, [ip, #0]    ; get old state
         STR     a2, [ip, #0]    ; mask the interrupt
+  [ {FALSE} ; reading GIC_CPU_INTACK has side effects on the interrupt system !?
         ; Check if we just disabled the active interrupt
         LDR     ip, [a3, #(MPU_INTC_CPU + GIC_CPU_INTACK)]
         CMP     ip, a1
@@ -188,13 +180,25 @@ HAL_IRQDisable
     [ DebugInterrupts
         MOVEQ   ip, #-1
         STREQ   ip, LastInterrupt_IRQ
+    ]
+  |
+        ; Clear any pending state of this source
+        STR     a2, [ip, #(GIC_DIST_PENDING_CLEAR - GIC_DIST_ENABLE_CLEAR)]
+        ; Was it active?
+        LDR     ip, [ip, #(GIC_DIST_ACTIVE_BIT - GIC_DIST_ENABLE_CLEAR)]
+        TST     ip, a2
+        STRNE   a1, [a3, #(MPU_INTC_CPU + GIC_CPU_EOI)]
+    [ DebugInterrupts
+        MOVNE   ip, #-1
+        STRNE   ip, LastInterrupt_IRQ
+    ]
   ]
         MSR     CPSR_c, a4      ; Re-enable interrupts
         AND     a1, lr, a2      ; Test if it was enabled or not
         Pull    "pc"
 
 HAL_IRQClear
-        ; This routine is used to clear the timer & vsync interrupts
+        ; This routine is also used to clear the timer interrupts
         ; It must also restart the INTC priority sorting, as it is called after every
         ; OS IRQ handler silences the interrupting device
  [ ExtraDebugInterrupts
@@ -214,7 +218,7 @@ HAL_IRQClear
         MOV     a2, #7          ; Clear all interrupts
         STR     a2, [a3, #GPT_IRQSTATUS]
 10
-        ; signal End Of Interrupt
+        ; Signal End Of Interrupt
         LDR     a2, MPU_INTC_Log
         STR     a1, [a2, #(MPU_INTC_CPU + GIC_CPU_EOI)]
         ; Data synchronisation barrier to make sure INTC gets the message
@@ -282,25 +286,12 @@ HAL_IRQStatus
         CMP     a1, #INTERRUPT_MAX
         MOVHS   a1, #0
         MOVHS   pc, lr
-        ; First we need to make sure this is an IRQ, not an FIQ?
-        MRS     a4, CPSR
-        ORR     a3, a4, #F32_bit+I32_bit
-        MSR     CPSR_c, a3
-        LDR     a2, MPU_INTC_Log
-;       ASSERT  INTCPS_ILR_SIZE = 4
-;       ADD     a3, a2, a1, LSL #2
-;       LDR     a3, [a3, #INTCPS_ILR]
-;       TST     a3, #1
-;       MOVNE   a1, #0 ; This is an FIQ, so it can't fire for IRQ
-;       MSRNE   CPSR_c, a4
-;       MOVNE   pc, lr
-        ; Now check if it's firing
 
+        LDR     a2, MPU_INTC_Log
         ADD     ip, a2, #(MPU_INTC_DIST + GIC_DIST_ACTIVE_BIT)
         MOV     a3, a1, LSR #5  ; index = intno / 32
         ADD     ip, ip, a3, LSL #2
         LDR     a3, [ip, #0]    ; get old state
-        MSR     CPSR_c, a4
         AND     a1, a1, #31     ; bit   = intno % 32
         MOV     a1, a3, LSR a1  ; Shift and invert so 1=active
         AND     a1, a1, #1      ; 0 = not firing, 1 = firing