Commit b619bcbf authored by Jeffrey Lee's avatar Jeffrey Lee
Browse files

Add support for recent U-Boot versions

Detail:
  hdr/PRCM:
  - added further definitions (not listed in older TRMs)
  s/Audio:
  - configure all GPIO pads used by audio system
    (for supporting latest U-Boot 2014-7)
  s/Boot:
  - added overflow check for address range
  s/RAM:
  - added overflow check for address range
  - address comparison with unsigned arithmetic
  s/RTC:
  - added initialisation code and pad configuration for TWL6030 RTC
    (for supporting latest U-Boot 2014-07)
  s/SDIO:
  - added pad configuration for LEDs used by SDIO
    (for supporting latest U-Boot 2014-07)
  s/USB:
  - removed unused code parts
  - use defines for controller types
  s/Video:
  - added pad configuration for DVI framer pin
  - enable DSS power and clock domain and DSS specific clocks
  - activate thermal sensor clock
  - wait for activated module in VideoDevice_Activate
    (for supporting latest U-Boot 2014-07)
Admin:
  Submission from Willi Theiss
  Tested on Panda ES rev B3 (Willi), Panda rev A6 (myself)


Version 0.36. Tagged as 'OMAP4-0_36'
parent 136ab5fd
/* (0.35)
/* (0.36)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.35
#define Module_MajorVersion_CMHG 0.36
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 20 Jul 2014
#define Module_Date_CMHG 04 Sep 2014
#define Module_MajorVersion "0.35"
#define Module_Version 35
#define Module_MajorVersion "0.36"
#define Module_Version 36
#define Module_MinorVersion ""
#define Module_Date "20 Jul 2014"
#define Module_Date "04 Sep 2014"
#define Module_ApplicationDate "20-Jul-14"
#define Module_ApplicationDate "04-Sep-14"
#define Module_ComponentName "OMAP4"
#define Module_ComponentPath "castle/RiscOS/Sources/HAL/OMAP4"
#define Module_FullVersion "0.35"
#define Module_HelpVersion "0.35 (20 Jul 2014)"
#define Module_LibraryVersionInfo "0:35"
#define Module_FullVersion "0.36"
#define Module_HelpVersion "0.36 (04 Sep 2014)"
#define Module_LibraryVersionInfo "0:36"
......@@ -238,6 +238,13 @@ PM_L4PER_UART4_WKDEP * &0158
RM_L4PER_UART4_CONTEXT * &015C
PM_L4PER_MMCSD5_WKDEP * &0160
RM_L4PER_MMCSD5_CONTEXT * &0164
RM_L4SEC_AES1_CONTEXT * &01A4
RM_L4SEC_AES2_CONTEXT * &01AC
RM_L4SEC_DES3DES_CONTEXT * &01B4
RM_L4SEC_PKA_CONTEXT * &01BC
RM_L4SEC_RNG_CONTEXT * &01C4
RM_L4SEC_SHA2MD5_CONTEXT * &01CC
RM_L4SEC_CRYPTODMA_CONTEXT * &01DC
; WKUP_PRM registers - relative to WKUP_PRM
RM_WKUP_L4WKUP_CONTEXT * &0024
......@@ -640,6 +647,16 @@ CM_L4PER_UART2_CLKCTRL * &0148
CM_L4PER_UART3_CLKCTRL * &0150
CM_L4PER_UART4_CLKCTRL * &0158
CM_L4PER_MMCSD5_CLKCTRL * &0160
CM_L4SEC_CLKSTCTRL * &0180
CM_L4SEC_STATICDEP * &0184
CM_L4SEC_DYNAMICDEP * &0188
CM_L4SEC_AES1_CLKCTRL * &01A0
CM_L4SEC_AES2_CLKCTRL * &01A8
CM_L4SEC_DES3DES_CLKCTRL * &01B0
CM_L4SEC_PKA_CLKCTRL * &01B8
CM_L4SEC_RNG_CLKCTRL * &01C0
CM_L4SEC_SHA2MD5_CLKCTRL * &01C8
CM_L4SEC_CRYPTODMA_CLKCTRL * &01D8
; RESTORE_CM2 registers - relative to RESTORE_CM2
CM_L3_1_CLKSTCTRL_RESTORE * &0000
......
......@@ -220,6 +220,20 @@ Audio_Init
DebugReg v2, "McPDM @ "
]
; Configure all PADs for McPDM and AUDIOPWRON pin
LDR a1, L4_Core_Log
LDR a2, =(L4_SYSCTRL_PADCONF_CORE - L4_Core)
ADD a1, a2, a1
ADD a1, a1, #0x100 ; add common offset
MOV a2, #0x03 ; output: Mode 3 (GPIO)
STRH a2, [a1, #0x020] ; GPIO_127 at offset 0x120
LDR a2, =0x01080108 ; inputs: IEN + PTD + Mode 0
LDR a3, =0x0118 ; input: IEN + PTU + Mode 0
STRH a2, [a1, #0x0006] ; ABE_PDM_UL_DATA
STRH a2, [a1, #0x0008] ; ABE_PDM_DL_DATA
STRH a3, [a1, #0x000A] ; ABE_PDM_FRAME
STR a2, [a1, #0x000C] ; ABE_PDM_LB_CLK + ABE_CLKS
; Before we go any further, enable module McPDM
LDR a1, L4_ClockMan_Log
ADD a1, a1, #CKGEN_CM1
......@@ -711,7 +725,7 @@ IRQHandle
DebugReg a2,"IRQHandle: IRQSTATUS="
Pull "sb,lr"
]
[ {FALSE}
[ {FALSE} ;{TRUE}
; Just clear the IRQ and ask for an audio reset
LDR a3, AudioRegs
MVN a2, #0
......
......@@ -106,7 +106,9 @@ rom_checkedout_ok
LDR a4, =(16 * 1024 * 1024) ; 16 MiB smallest size
MOV a4, a4, LSL a2 ; final size
AND a2, a3, #DMM_LISA_MAP_i_SYS_ADDR
ADD a3, a4, a2
; Check for overflow of address range
ADDS a3, a4, a2
LDRCS a3, =((4096 - 16) << 20) ; round down to next 16 MiB boundary
LDR a4, =&FFFFFFFF
ADD sp, a2, #4096 ; HAL spec says that (for software reset compliance only?) stack should be 4K into first block
MOV a1, #0
......
......@@ -58,7 +58,9 @@ get_end_of_ram
LDR a4, =(16 * 1024 * 1024) ; 16 MiB smallest size
MOV a4, a4, LSL a2 ; final size
AND a2, a3, #DMM_LISA_MAP_i_SYS_ADDR
ADD a1, a4, a2
; check for overflow of address range
ADDS a1, a4, a2
LDRCS a1, =((4096 - 16) << 20) ; round down to next 16 MiB boundary
MOV pc, lr
......@@ -132,7 +134,7 @@ clear_ram
AND a2, a3, #DMM_LISA_MAP_i_SYS_ADDR
SUB a1, v2, a2
CMP a1, a4
MOVGT a1, a4 ; Work out how much we're meant to be clearing
MOVHI a1, a4 ; Work out how much we're meant to be clearing
CMP a1, #0
BEQ %FT30
......
......@@ -41,7 +41,7 @@
IMPORT memcpy
; TWL6030 RTC IIC address
TPSRTC_IIC * &48
TPSRTC_IIC * (&48 * 2)
; Some RTC registers
SECONDS_REG * &00
......@@ -144,11 +144,11 @@ RTC_Init
MOV a3, #RTCSize
BL memcpy
STR sb, [a1, #RTCDeviceHAL_SB]
SUB sp, sp, #4 ; temp small buffer on stack
; check for external DS1338 chip on I2C4 bus
LDR v1, OSentries+4*OS_IICOpV ; for I2CBusRead/I2CBusWrite
MOV v2, #DS1338_IIC_BUS ; specify I2C bus
SUB sp, sp, #4 ; temp small buffer on stack
MOV a1, #DS1338_IIC_ADDR
MOV a3, #1
MOV a4, #DS_RTC_CTRL_REG
......@@ -175,7 +175,41 @@ RTC_Init
MOV a1, #HALDeviceID_RTC_DS1307 ; at least we are compatible to this one :-)
STRH a1, [a3, #HALDevice_ID]
B %FT50
10
; no external RTC ==> initialise TWL6030 RTC
; prepare GPIO pad for TWL6030 MSECURE input pin (allow write access to RTC)
LDR a1, L4_Wakeup_Log
LDR a2, =(L4_SYSCTRL_PADCONF_WKUP - L4_Wakeup)
ADD a1, a2, a1
LDR a2, =0x0002 ; output + Mode 2 (Reserved)
STRH a2, [a1, #0x0054] ; gpio_wk6
; check TWL6030 RTC state
LDR v1, OSentries+4*OS_IICOpV ; for TPSRead/TPSWrite
MOV a1, #TPSRTC_IIC
MOV a3, #1
MOV a4, #RTC_STATUS_REG
MOV a2, sp
BL TPSRead
CMP a1, #IICStatus_Completed
BNE %FT50
MOV a1, #TPSRTC_IIC
BL TPSWrite
; check for running clock and start it (if not running)
MOV a4, #RTC_CTRL_REG
MOV a1, #TPSRTC_IIC
BL TPSRead
LDRB a1, [a2]
TST a1, #RTC_CTRL_STOP_RTC_M
BNE %FT50
ORR a1, a1, #RTC_CTRL_STOP_RTC_M
STRB a1, [a2]
MOV a1, #TPSRTC_IIC
BL TPSWrite
50
ADD sp, sp, #4
Pull "v1-v2,lr"
......@@ -242,7 +276,7 @@ RTCReadTime
; time registers, NOT the alarm ones as stated by the manual!)
; 3. Read the time regs to read latched time.
; There's no need to clear GET_TIME either, as it is cleared automatically by the HW.
MOV a1, #TPSRTC_IIC*2
MOV a1, #TPSRTC_IIC
SUB sp, sp, #4 ; temp small buffer on stack
MOV a3, #1
MOV a4, #RTC_STATUS_REG
......@@ -258,14 +292,14 @@ RTCReadTime
Pull "v1,v3,sb,pc", NE
MOV ip, #(RTC_CTRL_GET_TIME_M + RTC_CTRL_STOP_RTC_M)
STR ip, [a2]
MOV a1, #TPSRTC_IIC*2
MOV a1, #TPSRTC_IIC
MOV a4, #RTC_CTRL_REG
BL TPSWrite
CMP a1, #IICStatus_Completed
MOVNE a1, #RTCRetCode_Error
ADD sp, sp, #4
Pull "v1,v3,sb,pc", NE
MOV a1, #TPSRTC_IIC*2
MOV a1, #TPSRTC_IIC
; We can read the time directly into the RTCTimeStruct buffer
ASSERT RTCTimeStruct_BCD_Minutes=RTCTimeStruct_BCD_Seconds+1
ASSERT RTCTimeStruct_BCD_Hours=RTCTimeStruct_BCD_Seconds+2
......@@ -304,7 +338,7 @@ RTCWriteTime
; the clock updating while it's being written to)
; 2. Write the new time values
; 3. Write 1 to RTC_CTRL_REG to start the clock
MOV a1, #TPSRTC_IIC*2
MOV a1, #TPSRTC_IIC
MOV ip, #0
STR ip, [sp,#-4]! ; temp small buffer on stack
MOV a3, #1
......@@ -315,7 +349,7 @@ RTCWriteTime
MOVNE a1, #RTCRetCode_Error
ADDNE sp, sp, #4
Pull "v1,v3,sb,pc", NE
MOV a1, #TPSRTC_IIC*2
MOV a1, #TPSRTC_IIC
; We can write the time directly from the RTCTimeStruct buffer
ASSERT RTCTimeStruct_BCD_Minutes=RTCTimeStruct_BCD_Seconds+1
ASSERT RTCTimeStruct_BCD_Hours=RTCTimeStruct_BCD_Seconds+2
......@@ -346,7 +380,7 @@ RTCWriteTime
STR a3, [sp]
MOV a2, sp
MOV a4, #RTC_CTRL_REG
MOV a1, #TPSRTC_IIC*2
MOV a1, #TPSRTC_IIC
BL TPSWrite
CMP a1, #IICStatus_Completed
ASSERT RTCRetCode_OK = IICStatus_Completed
......
......@@ -313,6 +313,14 @@ Activate_MMC1_Pandaboard ROUT
LDR sb, [a1, #SDHCISB]
SUB sp, sp, #4 ; buffer for TWL6030 register contents
; configure LEDs as gpio pins
LDR a4, L4_Wakeup_Log
LDR a2, =(L4_SYSCTRL_PADCONF_WKUP - L4_Wakeup)
ADD a4, a2, a4
MOV a3, #3 ; output: Mode 3 (GPIO)
STRH a3, [a4, #0x5A] ; gpio_wk7 == PB_LED_D1
STRH a3, [a4, #0x5C] ; gpio_wk8 == PB_LED_D2
; switch OFF LED D2
GPIO_PrepareC a3, a2, $PB_LED_D2
GPIO_SetAsOutput a3, a2, a4
......@@ -342,6 +350,17 @@ Activate_MMC1_PandaboardES ROUT
LDR sb, [a1, #SDHCISB]
SUB sp, sp, #4 ; buffer for TWL6030 register contents
; configure LEDs as gpio pins
LDR a4, L4_Core_Log
LDR a2, =(L4_SYSCTRL_PADCONF_CORE - L4_Core)
ADD a4, a2, a4
MOV a3, #3 ; output: Mode 3 (GPIO)
STRH a3, [a4, #0xF6] ; gpio_110 == PE_LED_D1
LDR a4, L4_Wakeup_Log
LDR a2, =(L4_SYSCTRL_PADCONF_WKUP - L4_Wakeup)
ADD a4, a2, a4
STRH a3, [a4, #0x5C] ; gpio_wk8 == PB_LED_D2
; switch OFF LED D2
GPIO_PrepareC a3, a2, $PB_LED_D2
GPIO_SetAsOutput a3, a2, a4
......
......@@ -45,9 +45,6 @@
IMPORT GPIOx_SetAsOutput
IMPORT GPIOx_SetOutput
; USB PHY power is controlled via GPIO
;USB2_PHY_GPIO * 147 -> board config
USB2_PHY_Reset_delay * 10000 ; 10msec
; GPIO pins for USB
GPIO_HUB_NRESET * 62
......@@ -61,6 +58,8 @@ USB_Init
Push "lr"
; Initialise USB
; This code is roughly the same as omap4_ehci_init() in the linux sources
; remark: there is no need to configure pins GPIO_HUB_POWER + GPIO_HUB_NRESET
; because it is already done by U-Boot (it uses USB itself)
; disable the power to the usb hub prior to init
MOV a1, #GPIO_HUB_POWER
......@@ -92,16 +91,6 @@ USB_Init
STR a2, [a1, #0xD4] ; USBB1_ULPIPHY_DAT6 (IO) + USBB1_ULPIPHY_DAT5 (IO)
STRH a2, [a1, #0xD8] ; USBB1_ULPIPHY_DAT7 (IO)
[ {FALSE}
; Linux does not do this
; set IO pins and O pins as output: GPIO_85, GPIO_88 .. GPIO_95
LDR a1, L4_GPIO3_Log
LDR a2, [a1, #GPIO_OE]
BIC a2, a2, #(0xFF << (88 - 64))
BIC a2, a2, #(1 << (85 - 64))
STR a2, [a1, #GPIO_OE]
]
; enable power to hub
MOV a1, #GPIO_HUB_POWER
MOV a2, #1
......@@ -156,12 +145,14 @@ HAL_USBControllerInfo
MOVHI pc, lr
BEQ %FT10
; Fill in the usbinfo struct
MOV a1, #1 ; EHCI
MOV a1, #HALUSBControllerType_EHCI
STR a1, [a2, #USBINFO_TYPE]
CMP a3, #USBINFO_SIZEOF
MOV a1, #USBINFO_SIZEOF
MOVLO pc, lr
MOV a4, #USBINFO_FLAG_32bit_Regs ; EHCI did seem to work OK without forcing 32bit register access, but it is technically needed so I'll leave it set.
; EHCI did seem to work OK without forcing 32bit register access,
; but it is technically needed so I'll leave it set.
MOV a4, #USBINFO_FLAG_32bit_Regs
STR a4, [a2, #USBINFO_FLAGS]
LDR a4, L4_USB_Host_Log
ADD a4, a4, #EHCI_BASE
......@@ -170,7 +161,7 @@ HAL_USBControllerInfo
STR a4, [a2, #USBINFO_DEVNO]
MOV pc, lr
10
MOV a1, #2 ; MUSBMHDRC
MOV a1, #HALUSBControllerType_MUSBMHDRC
STR a1, [a2, #USBINFO_TYPE]
CMP a3, #USBINFO_SIZEOF
MOV a1, #USBINFO_SIZEOF
......
......@@ -90,17 +90,16 @@
Video_Init
Push "lr"
; Configure GPIO pins so we can turn the DVI framer on/off
LDRB a1, [sb, #BoardConfig_VideoGPIO]
CMP a1, #255
MOV a2, #0
BLNE GPIOx_SetAsOutput ; Turn DVI framer off
; configure GPIO pins as DISPC2 signals
; Configure GPIO pins as DISPC2 signals
LDR a1, L4_Core_Log
LDR a2, =(L4_SYSCTRL_PADCONF_CORE - L4_Core)
ADD a1, a2, a1
ADD a3, a1, #0x100
; Configure DVI framer pin (Panda)
LDRB a4, [sb, #BoardConfig_VideoGPIO]
CMP a4, #0 ; check for GPIO_0
LDREQ a4, =0x11B ; output: IEN + PullUp + Mode 3 (GPIO)
STREQH a4, [a3, #0x084] ; GPIO_0 at offset 0x184
LDR a2, =0x00050005
STRH a2, [a3, #0x0D4] ; GPIO_191/DISPC2_DATA0
STR a2, [a1, #0x1D0] ; GPIO_190/DISPC2_DATA1 + GPIO_28/DISPC2_DATA2
......@@ -118,30 +117,34 @@ Video_Init
STR a2, [a1, #0x164] ; GPIO_160/DISPC2_DATA21 + GPIO_159/DISPC2_DATA22
STRH a2, [a3, #0x062] ; GPIO_158/DISPC2_DATA23
[ {FALSE}
; Linux does not do this
; Configure GPIO pins so we can turn the DVI framer on/off
LDRB a1, [sb, #BoardConfig_VideoGPIO]
CMP a1, #255
MOV a2, #0
BLNE GPIOx_SetAsOutput ; Turn DVI framer off
; Enable DSS power domain
LDR a1, L4_PowerMan_Log
ADD a1, a1, #DSS_PRM
LDR a2, [a1, #PM_DSS_PWRSTCTRL]
ORR a2, a2, #3 ; ON state
STR a2, [a1, #PM_DSS_PWRSTCTRL]
; set all pins as output
; GPIO_14 .. GPIO_28
LDR a1, L4_GPIO1_Log
LDR a2, [a1, #GPIO_OE]
BIC a2, a2, #(0xFF << (14 - 0))
BIC a2, a2, #(0x7F << (22 - 0))
STR a2, [a1, #GPIO_OE]
; GPIO_158 .. GPIO_159
LDR a1, L4_GPIO5_Log
LDR a2, [a1, #GPIO_OE]
BIC a2, a2, #(0x03 << (158 - 4 * 32))
STR a2, [a1, #GPIO_OE]
; GPIO_160 .. GPIO_168
LDR a1, L4_GPIO6_Log
LDR a2, [a1, #GPIO_OE]
BIC a2, a2, #(0xFF << (160 - 5 * 32))
BIC a2, a2, #(0x01 << (168 - 5 * 32))
; GPIO_190 .. GPIO_191
BIC a2, a2, #(0x03 << (190 - 5 * 32))
STR a2, [a1, #GPIO_OE]
]
; Activate Thermal Sensor Clock (not done by U-Boot 2014)
; Is there a better place to do it?
; I'm doing it here because it is the only location where L4_PowerMan is used.
ADD a1, a1, #(WKUP_CM - DSS_PRM)
LDR a2, [a1, #CM_WKUP_BANDGAP_CLKCTRL]
ORR a2, a2, #(1 << 8) ; OPTFCLKEN_TS_FCLK
STR a2, [a1, #CM_WKUP_BANDGAP_CLKCTRL]
; Activate DSS specific clocks
LDR a1, L4_ClockMan2_Log
ADD a1, a1, #DSS_CM2
LDR a2, =((0xF << 8) + 2) ; OPTFCLKEN_* + enable module
STR a2, [a1, #CM_DSS_DSS_CLKCTRL]
MOV a2, #2 ; SW_WKUP
STR a2, [a1, #CM_DSS_CLKSTCTRL]
Pull "pc"
......@@ -213,9 +216,17 @@ VideoDevice_Activate
LDR a1, L4_ClockMan2_Log
ADD a1, a1, #DSS_CM2
LDR a2, [a1, #CM_DSS_DSS_CLKCTRL]
ANDS a2, a2, #((1 << 18) + (3 << 16)) ; STDBST | IDLEST
MOVNE a2, #2 ; SW_WKUP
STRNE a2, [a1, #CM_DSS_CLKSTCTRL]
ANDS a2, a2, #(3 << 16) ; IDLEST
BEQ %FT10
MOV a2, #2 ; SW_WKUP
STR a2, [a1, #CM_DSS_CLKSTCTRL]
; Wait until module is active
05
LDR a2, [a1, #CM_DSS_DSS_CLKCTRL]
ANDS a2, a2, #(3 << 16) ; IDLEST
BNE %BT05
10
MOV a1, #1
EXIT
......
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