Commit b43663f6 authored by Robert Sprowson's avatar Robert Sprowson
Browse files

Add SmartReflex driver

Submission from Willi Theiss.
Built, but not tested here.

Version 0.20. Tagged as 'OMAP4-0_20'
parent ff60f3e7
......@@ -17,7 +17,7 @@
COMPONENT = OMAP-4 HAL
TARGET = OMAP4
OBJS = Top Boot Interrupts Timers CLib CLibAsm Stubs UART Debug PRCM Video USB I2C RTC SDMA TPS Audio GPIO GPMC NVMemory KbdScan SDIO #CPUClk
OBJS = Top Boot Interrupts Timers CLib CLibAsm Stubs UART Debug PRCM Video USB I2C RTC SDMA TPS Audio GPIO GPMC NVMemory KbdScan SDIO SR44x
USBDIR = <Lib$Dir>.USB
HDRS =
......
/* (0.19)
/* (0.20)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.19
#define Module_MajorVersion_CMHG 0.20
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 01 Sep 2013
#define Module_Date_CMHG 02 Sep 2013
#define Module_MajorVersion "0.19"
#define Module_Version 19
#define Module_MajorVersion "0.20"
#define Module_Version 20
#define Module_MinorVersion ""
#define Module_Date "01 Sep 2013"
#define Module_Date "02 Sep 2013"
#define Module_ApplicationDate "01-Sep-13"
#define Module_ApplicationDate "02-Sep-13"
#define Module_ComponentName "OMAP4"
#define Module_ComponentPath "castle/RiscOS/Sources/HAL/OMAP4"
#define Module_FullVersion "0.19"
#define Module_HelpVersion "0.19 (01 Sep 2013)"
#define Module_LibraryVersionInfo "0:19"
#define Module_FullVersion "0.20"
#define Module_HelpVersion "0.20 (02 Sep 2013)"
#define Module_LibraryVersionInfo "0:20"
; Copyright 2013 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
[ :LNOT: :DEF: __HAL_SR44X_HDR__
GBLL __HAL_SR44X_HDR__
GET Hdr:CPUClkDevice
GET hdr.irqs44xx
; SmartReflex registers - relative to L4_SR_MPU,L4_SR_IVA,L4_SR_CORE
SR44x_SRCONFIG * &00
SR44x_SRSTATUS * &04
SR44x_SENVAL * &08
SR44x_SENMIN * &0C
SR44x_SENMAX * &10
SR44x_SENAVG * &14
SR44x_AVGWEIGHT * &18
SR44x_NVALUERECIPROCAL * &1C
SR44x_IRQSTATUS_RAW * &24
SR44x_IRQSTATUS * &28
SR44x_IRQENABLE_SET * &2C
SR44x_IRQENABLE_CLR * &30
SR44x_SENERROR * &34
SR44x_ERRCONFIG * &38
; bits in SRCONFIG register
SRCONFIG_SENPENABLE * (1 << 0)
SRCONFIG_SENNENABLE * (1 << 1)
SRCONFIG_MINMAXAVGENABLE * (1 << 8)
SRCONFIG_ERRORGENERATORENABLE * (1 << 9)
SRCONFIG_SENENABLE * (1 << 10)
SRCONFIG_SRENABLE * (1 << 11)
SRCONFIG_SRCLKLENGTH_MSK * (0x3FF << 12)
SRCONFIG_SRCLKLENGTH_SHIFT * 12
SRCONFIG_SRCLKLENGTH_WIDTH * 10
SRCONFIG_ACCUMDATA_MSK * (0x3FF << 22)
SRCONFIG_ACCUMDATA_SHIFT * 22
SRCONFIG_ACCUMDATA_WIDTH * 10
; bits in SRSTATUS register
SRSTATUS_MINMAXAVGACCUMVALID * (1 << 0)
SRSTATUS_ERRORGENERATORVALID * (1 << 1)
SRSTATUS_MINMAXAVGVALID * (1 << 2)
SRSTATUS_AVGERRVALID * (1 << 3)
; bits in AVGWEIGHT register
AVGWEIGHT_SENNAVGWEIGHT * (3 << 0)
AVGWEIGHT_SENPAVGWEIGHT * (3 << 2)
; bits in NVALUERECIPROCAL register
NVALUERECIPROCAL_SENNRN * (255 << 0)
NVALUERECIPROCAL_SENPRN * (255 << 8)
NVALUERECIPROCAL_SENNGAIN * ( 15 << 16)
NVALUERECIPROCAL_SENPGAIN * ( 15 << 20)
; bits in IRQ registers (IRQSTATUS_RAW, IRQSTATUS, IRQENABLE_SET, IRQENABLE_CLR)
SRIRQ_MCUDISABLEACK * (1 << 0)
SRIRQ_MCUBOUNDS * (1 << 1)
SRIRQ_MCUVALID * (1 << 2)
SRIRQ_MCUACCUM * (1 << 3)
; bits in SENERROR register
SENERROR_SENERROR * (255 << 0)
SENERROR_AVGERROR * (255 << 8)
; bits in ERRCONFIG register
ERRCONFIG_ERRMINLIMIT * (255 << 0)
ERRCONFIG_ERRMAXLIMIT * (255 << 8)
ERRCONFIG_ERRWEIGHT * (7 << 16)
ERRCONFIG_VPBOUNDSINTENABLE * (1 << 22)
ERRCONFIG_VPBOUNDSINTSTATENA * (1 << 23)
ERRCONFIG_IDLEMODE * (3 << 24)
ERRCONFIG_IDLEMODE_FORCE * (0 << 24)
ERRCONFIG_IDLEMODE_NONE * (1 << 24)
ERRCONFIG_IDLEMODE_SMART * (2 << 24)
ERRCONFIG_IDLEMODE_SMART_WKUP * (3 << 24)
ERRCONFIG_IDLEMODE_SHIFT * 24
ERRCONFIG_IDLEMODE_WIDTH * 2
ERRCONFIG_WAKEUPENABLE * (1 << 26)
; eFuse registers containing SmartReflex parameters - relative to L4_SYSCTRL_GENERAL_CORE
CONTROL_STD_FUSE_DIE_ID_0 * &0200
CONTROL_ID_CODE * &0204
CONTROL_STD_FUSE_DIE_ID_1 * &0208
CONTROL_STD_FUSE_DIE_ID_2 * &020C
CONTROL_STD_FUSE_DIE_ID_3 * &0210
CONTROL_STD_FUSE_PROD_ID_0 * &0214
CONTROL_STD_FUSE_PROD_ID_1 * &0218
CONTROL_STD_FUSE_USB_CONF * &021C
CONTROL_STD_FUSE_CONF * &0220
CONTROL_STD_FUSE_OPP_VDD_WKUP * &0228
CONTROL_STD_FUSE_OPP_VDD_IVA_0 * &022C
CONTROL_STD_FUSE_OPP_VDD_IVA_1 * &0230
CONTROL_STD_FUSE_OPP_VDD_IVA_2 * &0234
CONTROL_STD_FUSE_OPP_VDD_IVA_3 * &0238
CONTROL_STD_FUSE_OPP_VDD_MPU_0 * &0240
CONTROL_STD_FUSE_OPP_VDD_MPU_1 * &0244
CONTROL_STD_FUSE_OPP_VDD_MPU_2 * &0248
CONTROL_STD_FUSE_OPP_VDD_MPU_3 * &024C
CONTROL_STD_FUSE_OPP_VDD_CORE_0 * &0254
CONTROL_STD_FUSE_OPP_VDD_CORE_1 * &0258
CONTROL_STD_FUSE_OPP_VDD_CORE_2 * &025C
CONTROL_STD_FUSE_OPP_BGAP * &0260
CONTROL_STD_FUSE_OPP_DPLL_0 * &0264
CONTROL_STD_FUSE_OPP_DPLL_1 * &0268
; OMAP44xx control eFuse offsets
OMAP44XX_CONTROL_FUSE_IVA_OPP50 * &022C
OMAP44XX_CONTROL_FUSE_IVA_OPP100 * &022F
OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO * &0232
OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO * &0235
OMAP44XX_CONTROL_FUSE_IVA_OPPNITROSB * &0238
OMAP44XX_CONTROL_FUSE_MPU_OPP50 * &0240
OMAP44XX_CONTROL_FUSE_MPU_OPP100 * &0243
OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO * &0246
OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO * &0249
OMAP44XX_CONTROL_FUSE_MPU_OPPNITROSB * &024C
OMAP44XX_CONTROL_FUSE_CORE_OPP50 * &0254
OMAP44XX_CONTROL_FUSE_CORE_OPP100 * &0257
OMAP44XX_CONTROL_FUSE_CORE_OPP119 * &025A
; IRQs
SR1_IRQ * OMAP44XX_IRQ_SR_MPU
SR2_IRQ * OMAP44XX_IRQ_SR_CORE
SR3_IRQ * OMAP44XX_IRQ_SR_IVA
; Fixed values from Linux sources
SR44x_ACCUMDATA * &1F4 ; 5ms accumulator time window
SR44x_SENNAVGWEIGHT * 1
SR44x_SENPAVGWEIGHT * 1
SR44x_ERRWEIGHT * 4
SR44x_ERRMAXLIMIT * 2
; OPP table format for the SmartReflex driver
^ 0
SR44x_OPPTbl_MHz # 2 ; Max MHz value for this voltage
SR44x_OPPTbl_VDD # 1 ; Required VDD value, in VDD1_VSEL format
SR44x_OPPTbl_CLKOUT_M2 # 1 ; Required CLKOUT_M2 value
SR44x_OPPTbl_NVALUERECIPROCAL # 4 ; Required NVALUERECIPROCAL value
SR44x_OPPTbl_ERRCONFIG # 3 ; Required SR ERRCONFIG value (bits 0-18)
SR44x_OPPTbl_ERRGAIN # 1 ; Required VP ERRGAIN value
SR44x_OPPTbl_DPLL_VAL # 4 ; CM_CLKSEL_DPLL_MPU value
SR44x_OPPTbl_Size # 0 ; Size of each entry
SR44x_OPPTbl_Format * 1 ; Format number as returned by SR44x_Override
SR44x_OPPTbl_Max * 5 ; Max number of entries we support
; Workspace
^ 0, a1
; Public bits
SR44xDevice # HALDevice_CPUClk_Size_0_1 ; support API 0.1
; Private bits
SR44xWorkspace # 4 ; HAL workspace pointer
SR44xNewSpeed # 4 ; Re-entrancy flag. -1 if idle, desired table idx if in process of
; changing CPU speed. Allows SR44x_Get to finish changing the speed
; if it gets called in the middle of a change. (Note somewhat
; redundant since SR44x code currently avoids re-entrancy)
SR44xCurSpeed # 4 ; Current table idx
SR44xOPPTblSize # 4 ; Number of entries in table
SR44xOPPTbl # SR44x_OPPTbl_Size * SR44x_OPPTbl_Max ; OPP table
SR44x_DeviceSize * :INDEX: @
SR44x_WorkspaceSize * SR44x_DeviceSize
] ; __HAL_SR44X_HDR__
END
......@@ -21,6 +21,7 @@
GET hdr.Audio
GET hdr.I2C
GET hdr.board
GET hdr.SR44x
GET <Lib$Dir>.USB.hdr.usbhal
GET Hdr:SDHCIDevice
GET Hdr:GPIODevice
......@@ -98,6 +99,7 @@ VideoDevice # Video_DeviceSize
VideoBoardConfig # VideoBoardConfig_Size
AudioWS # Audio_WorkspaceSize
CPUClkWS # SR44x_WorkspaceSize
GPIOWS # HALDevice_GPIO_Size
NVRAMWS # HALDeviceSize
......
......@@ -48,6 +48,9 @@ FIQDebug SETL {FALSE}
GBLL MoreDebug
MoreDebug SETL Debug :LAND: {FALSE}
GBLL UseSR44x
UseSR44x SETL {TRUE}
AREA |Asm$$Code|, CODE, READONLY, PIC
EXPORT rom_checkedout_ok
......@@ -58,6 +61,8 @@ MoreDebug SETL Debug :LAND: {FALSE}
IMPORT DebugHALPrintByte
IMPORT RTC_Init
IMPORT DebugCallstack
IMPORT SR44x_Init
IMPORT SR44x_Exit
; v8 is used as pointer to RISC OS entry table throughout pre-MMU stage.
MACRO
......@@ -730,6 +735,9 @@ HAL_InitDevices
Entry "v1-v3"
DebugTime a1, "HAL_InitDevices @ "
; Common HAL devices
[ UseSR44x
BL SR44x_Init
]
BL NVMemory_InitDevice
BL RTC_Init
BL SDMA_Init
......@@ -871,6 +879,11 @@ HAL_PhysTable
DCD 0
HAL_Reset
[ UseSR44x
Push "a1"
BL SR44x_Exit
Pull "a1"
]
; Reset or power off?
CMP a1, #0
BNE %FT10
......
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