Commit a4c0a9e8 authored by Robert Sprowson's avatar Robert Sprowson
Browse files

Bulk expand of tabs.

Helps to make tracking changes between OMAP3 and OMAP4 less eye watering, but otherwise functionally the same as 0.06.

Version 0.07. Tagged as 'OMAP4-0_07'
parent 67202e54
hdr/** gitlab-language=armasm linguist-language=armasm linguist-detectable=true
s/** gitlab-language=armasm linguist-language=armasm linguist-detectable=true
c/** gitlab-language=c linguist-language=c linguist-detectable=true
h/** gitlab-language=c linguist-language=c linguist-detectable=true
/* (0.06)
/* (0.07)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.06
#define Module_MajorVersion_CMHG 0.07
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 25 Mar 2012
#define Module_MajorVersion "0.06"
#define Module_Version 6
#define Module_MajorVersion "0.07"
#define Module_Version 7
#define Module_MinorVersion ""
#define Module_Date "25 Mar 2012"
......@@ -18,6 +18,6 @@
#define Module_ComponentName "OMAP4"
#define Module_ComponentPath "castle/RiscOS/Sources/HAL/OMAP4"
#define Module_FullVersion "0.06"
#define Module_HelpVersion "0.06 (25 Mar 2012)"
#define Module_LibraryVersionInfo "0:6"
#define Module_FullVersion "0.07"
#define Module_HelpVersion "0.07 (25 Mar 2012)"
#define Module_LibraryVersionInfo "0:7"
/* Copyright 2011 Castle Technology Ltd
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __HAL_NVMEM_H__
#define __HAL_NVMEM_H__
int NVMem_C_read(ws *wsptr);
uint GetUInt(union data_area *da, uint uiOfs);
uint GetUShort(union data_area *da, uint uiOfs);
bool ReadBlockAbsolute(ws *wsptr, uint uiBlockNum, union data_area *da);
bool ReadBlockOfPartition(ws *wsptr, uint uiBlockNum, union data_area *da);
void print_block_data(union data_area *da);
#endif /* __HAL_NVMEM_H__ */
/* Copyright 2011 Castle Technology Ltd
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdio.h>
#include <stdbool.h>
#include <string.h>
__global_reg(6) void *sb;
typedef unsigned int uint;
typedef unsigned char uchar;
typedef union data_area
{
unsigned int word[128];
unsigned char byte[512];
}data_area;
typedef struct
{
// NOTE - THIS STRUCT MUST BE IDENTICAL TO THE
// NVMem_workspace DECLARATION IN StaticWS
volatile uint* PRCM_CM_ICLKEN1_CORE;
volatile uint* PRCM_CM_FCLKEN1_CORE;
volatile uint* MMCHS1_SYSCONFIG;
volatile uint* MMCHS1_SYSSTATUS;
volatile uint* MMCHS1_CSRE;
volatile uint* MMCHS1_SYSTEST;
volatile uint* MMCHS1_CON;
volatile uint* MMCHS1_PWCNT;
volatile uint* MMCHS1_BLK;
volatile uint* MMCHS1_ARG;
volatile uint* MMCHS1_CMD;
volatile uint* MMCHS1_RSP10;
volatile uint* MMCHS1_RSP32;
volatile uint* MMCHS1_RSP54;
volatile uint* MMCHS1_RSP76;
volatile uint* MMCHS1_DATA;
volatile uint* MMCHS1_PSTATE;
volatile uint* MMCHS1_HCTL;
volatile uint* MMCHS1_SYSCTL;
volatile uint* MMCHS1_STAT;
volatile uint* MMCHS1_IE;
volatile uint* MMCHS1_ISE;
volatile uint* MMCHS1_AC12;
volatile uint* MMCHS1_CAPA;
volatile uint* MMCHS1_CUR;
volatile uint* MMCHS1_REV;
uint CardType;
uint volume_base;
uint BPB_BytsPerSec;
uint BPB_SecPerClus;
uint bytespercluster;
uint BPB_RsvdSecCnt;
uint offset_to_FAT1;
uint BPB_NumFATs;
uint BPB_RootEntCnt;
uint BPB_TotSec16;
uint RootDirSectors;
uint BPB_FATSz16;
uint BPB_FATSz32;
uint FATSz;
uint offset_to_root_dir;
uint BPB_TotSec32;
uint TotSec;
uint DataSec;
uint CountOfClusters;
uint cluster0base;
uint BPB_RootClus;
uint bytesperFATentry;
uint FirstDataSector;
uint FATType;
uchar NVRAMCache[2048];
} ws;
#define FATTYPE_UNKNOWN 0
#define FATTYPE_FAT12 1
#define FATTYPE_FAT16 2
#define FATTYPE_FAT32 3
#define CARDTYPE_UNKNOWN 0
#define CARDTYPE_SD 1
#define CARDTYPE_SDHC 2
#define CARDTYPE_MMC 3
//#define DEBUG_ENABLED /* Global debug switch */
#ifdef DEBUG_ENABLED
#define dprintf printf
#else
#define dprintf(...) {}
#endif
/* Copyright 2011 Castle Technology Ltd
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
int FindDirectoryEntry (ws* wsptr, char FileName[], union data_area* da);
bool GetLongName (ws* wsptr, char long_name[], union data_area* da, uint* entry, int* Block, uint* Cluster);
void GetLongNameFragment (char frag_name[], union data_area* da, uint offset, uint num_chars);
bool ReadBlockClustered (ws* wsptr, uint* cluster, uint* offset, union data_area* da);
uint FirstSectorOfCluster (ws* wsptr, uint cluster);
uint ThisFATSecNum (ws* wsptr, uint cluster);
uint ThisFATEntOffset (ws* wsptr, uint cluster);
uint NextCluster (ws* wsptr, uint cluster);
bool ReadRootDirectoryBlock (ws* wsptr, int* Block, uint* Cluster, union data_area* da);
This diff is collapsed.
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......@@ -13,238 +13,238 @@
; limitations under the License.
;
[ :LNOT: :DEF: __HAL_GPIO_HDR__
GBLL __HAL_GPIO_HDR__
[ :LNOT: :DEF: __HAL_GPIO_HDR__
GBLL __HAL_GPIO_HDR__
GET hdr.irqs44xx
GET hdr.irqs44xx
; GPIO registers - relative to L4_GPIO1, L4_GPIO2, L4_GPIO3, etc.
GPIO_REVISION * &000
GPIO_SYSCONFIG * &010
GPIO_IRQSTATUS_RAW_0 * &024
GPIO_IRQSTATUS_RAW_1 * &028
GPIO_IRQSTATUS_0 * &02C
GPIO_IRQSTATUS_1 * &030
GPIO_IRQSTATUS_SET_0 * &034
GPIO_IRQSTATUS_SET_1 * &038
GPIO_IRQSTATUS_CLR_0 * &03C
GPIO_IRQSTATUS_CLR_1 * &040
GPIO_IRQWAKEN_0 * &044
GPIO_IRQWAKEN_1 * &048
GPIO_SYSTATUS * &114
GPIO_IRQSTATUS1 * &118
GPIO_IRQENABLE1 * &11C
GPIO_WAKEUPENABLE * &120
GPIO_IRQSTATUS2 * &128
GPIO_IRQENABLE2 * &12C
GPIO_CTRL * &130
GPIO_OE * &134
GPIO_DATAIN * &138
GPIO_DATAOUT * &13C
GPIO_LEVELDETECT0 * &140
GPIO_LEVELDETECT1 * &144
GPIO_RISINGDETECT * &148
GPIO_FALLINGDETECT * &14C
GPIO_DEBOUNCEENABLE * &150
GPIO_DEBOUNCINGTIME * &154
GPIO_CLEARIRQENABLE1 * &160
GPIO_SETIRQENABLE1 * &164
GPIO_CLEARIRQENABLE2 * &170
GPIO_SETIRQENABLE2 * &174
GPIO_CLEARWKUPENA * &180
GPIO_SETWKUENA * &184
GPIO_CLEARDATAOUT * &190
GPIO_SETDATAOUT * &194
GPIO_PIN_MAX * 192
GPIO_REVISION * &000
GPIO_SYSCONFIG * &010
GPIO_IRQSTATUS_RAW_0 * &024
GPIO_IRQSTATUS_RAW_1 * &028
GPIO_IRQSTATUS_0 * &02C
GPIO_IRQSTATUS_1 * &030
GPIO_IRQSTATUS_SET_0 * &034
GPIO_IRQSTATUS_SET_1 * &038
GPIO_IRQSTATUS_CLR_0 * &03C
GPIO_IRQSTATUS_CLR_1 * &040
GPIO_IRQWAKEN_0 * &044
GPIO_IRQWAKEN_1 * &048
GPIO_SYSTATUS * &114
GPIO_IRQSTATUS1 * &118
GPIO_IRQENABLE1 * &11C
GPIO_WAKEUPENABLE * &120
GPIO_IRQSTATUS2 * &128
GPIO_IRQENABLE2 * &12C
GPIO_CTRL * &130
GPIO_OE * &134
GPIO_DATAIN * &138
GPIO_DATAOUT * &13C
GPIO_LEVELDETECT0 * &140
GPIO_LEVELDETECT1 * &144
GPIO_RISINGDETECT * &148
GPIO_FALLINGDETECT * &14C
GPIO_DEBOUNCEENABLE * &150
GPIO_DEBOUNCINGTIME * &154
GPIO_CLEARIRQENABLE1 * &160
GPIO_SETIRQENABLE1 * &164
GPIO_CLEARIRQENABLE2 * &170
GPIO_SETIRQENABLE2 * &174
GPIO_CLEARWKUPENA * &180
GPIO_SETWKUENA * &184
GPIO_CLEARDATAOUT * &190
GPIO_SETDATAOUT * &194
GPIO_PIN_MAX * 192
; Flags for GPIOx_SetAndEnableIRQ
GPIO_LEVELDETECT0_FLAG * 1
GPIO_LEVELDETECT1_FLAG * 2
GPIO_RISINGDETECT_FLAG * 4
GPIO_FALLINGDETECT_FLAG * 8
GPIO_LEVELDETECT0_FLAG * 1
GPIO_LEVELDETECT1_FLAG * 2
GPIO_RISINGDETECT_FLAG * 4
GPIO_FALLINGDETECT_FLAG * 8
; interrupt number of lowest GPIO port
GPIO1_IRQ_NO * OMAP44XX_IRQ_GPIO1
GPIO1_IRQ_NO * OMAP44XX_IRQ_GPIO1
; TWL/TPS GPIO registers
TPS_GPIODATAIN1 * &98 ; *3
TPS_GPIODATADIR1 * &9B ; *3
TPS_GPIODATAOUT1 * &9E ; *3
TPS_CLEARGPIODATAOUT1 * &A1 ; *3
TPS_SETGPIODATAOUT1 * &A4 ; *3
TPS_GPIO_DEBEN1 * &A7 ; *3
TPS_GPIO_CTRL * &AA
TPS_GPIOPUPCTR1 * &AB ; *5
TPS_GPIO_ISR1A * &B1 ; *3
TPS_GPIO_IMR1A * &B4 ; *3
TPS_GPIO_ISR1B * &B7 ; *3
TPS_GPIO_IMR1B * &BA ; *3
TPS_GPIO_EDR1 * &C0 ; *5
TPS_GPIO_SIH_CTRL * &C5
TPS_PMBR1 * &92
TPS_PMBR2 * &93
TPSGPIO_IIC * &49
TPS_GPIO_PIN_MAX * 17
TPS_GPIODATAIN1 * &98 ; *3
TPS_GPIODATADIR1 * &9B ; *3
TPS_GPIODATAOUT1 * &9E ; *3
TPS_CLEARGPIODATAOUT1 * &A1 ; *3
TPS_SETGPIODATAOUT1 * &A4 ; *3
TPS_GPIO_DEBEN1 * &A7 ; *3
TPS_GPIO_CTRL * &AA
TPS_GPIOPUPCTR1 * &AB ; *5
TPS_GPIO_ISR1A * &B1 ; *3
TPS_GPIO_IMR1A * &B4 ; *3
TPS_GPIO_ISR1B * &B7 ; *3
TPS_GPIO_IMR1B * &BA ; *3
TPS_GPIO_EDR1 * &C0 ; *5
TPS_GPIO_SIH_CTRL * &C5
TPS_PMBR1 * &92
TPS_PMBR2 * &93
TPSGPIO_IIC * &49
TPS_GPIO_PIN_MAX * 17
; TWL/TPS LED registers
; (we treat these as extra output-only GPIOs, like Linux)
TPS_LEDEN * &EE
TPS_PWMAON * &EF
TPS_PWMAOFF * &F0
TPS_PWMBON * &F1
TPS_PWMBOFF * &F2
TPS_LEDEN * &EE
TPS_PWMAON * &EF
TPS_PWMAOFF * &F0
TPS_PWMBON * &F1
TPS_PWMBOFF * &F2
TPSLED_IIC * &4A
TPSLED_IIC * &4A
TPS_LED_PIN_MAX * 2
TPS_LED_PIN_MAX * 2
; OMAP GPIO related macros
; All assume sb = HAL workspace
; Prepare for GPIO operations (constant pin)
; In:
; $num = constant GPIO pin number
; $cc = condition code
; Out:
; $regs = GPIO register block ptr
; $mask = bit mask for pin
MACRO
GPIO_PrepareC $regs, $mask, $num, $cc
ASSERT $regs <> $mask
ASSERT $num < GPIO_PIN_MAX
LDR$cc $regs, L4_GPIO_Table+4*($num>>5)
MOV$cc $mask, #1 :SHL: ($num :AND: 31)
MEND
; Prepare for GPIO operations (register pin)
; In:
; $num = register containing GPIO pin number
; $cc = condition code
; $tmp = optional temp register to avoid clobbering $num
; Out:
; $regs = GPIO register block ptr
; $mask = bit mask for pin
; $num corrupted, unless $tmp specified
MACRO
GPIO_PrepareR $regs, $mask, $num, $cc, $tmp
ASSERT $regs <> $mask
[ "$tmp" = ""
ASSERT $mask <> $num
[ $regs = $num
EOR$cc $num, $num, #31
MOV$cc $mask, #&80000000
MOV$cc $mask, $mask, ROR $num
MOV$cc $regs, $num, LSR #5
ADD$cc $regs, sb, $regs, LSL #2
LDR$cc $regs, [$regs, #:INDEX:L4_GPIO_Table]
; Prepare for GPIO operations (constant pin)
; In:
; $num = constant GPIO pin number
; $cc = condition code
; Out:
; $regs = GPIO register block ptr
; $mask = bit mask for pin
MACRO
GPIO_PrepareC $regs, $mask, $num, $cc
ASSERT $regs <> $mask
ASSERT $num < GPIO_PIN_MAX
LDR$cc $regs, L4_GPIO_Table+4*($num>>5)
MOV$cc $mask, #1 :SHL: ($num :AND: 31)
MEND
; Prepare for GPIO operations (register pin)
; In:
; $num = register containing GPIO pin number
; $cc = condition code
; $tmp = optional temp register to avoid clobbering $num
; Out:
; $regs = GPIO register block ptr
; $mask = bit mask for pin
; $num corrupted, unless $tmp specified
MACRO
GPIO_PrepareR $regs, $mask, $num, $cc, $tmp
ASSERT $regs <> $mask
[ "$tmp" = ""
ASSERT $mask <> $num
[ $regs = $num
EOR$cc $num, $num, #31
MOV$cc $mask, #&80000000
MOV$cc $mask, $mask, ROR $num
MOV$cc $regs, $num, LSR #5
ADD$cc $regs, sb, $regs, LSL #2
LDR$cc $regs, [$regs, #:INDEX:L4_GPIO_Table]
|
; Slightly better instruction ordering
MOV$cc $regs, $num, LSR #5
EOR$cc $num, $num, #31
ADD$cc $regs, sb, $regs, LSL #2
MOV$cc $mask, #&80000000
LDR$cc $regs, [$regs, #:INDEX:L4_GPIO_Table]
MOV$cc $mask, $mask, ROR $num
]
|
; Slightly better instruction ordering
MOV$cc $regs, $num, LSR #5
EOR$cc $num, $num, #31
ADD$cc $regs, sb, $regs, LSL #2
MOV$cc $mask, #&80000000
LDR$cc $regs, [$regs, #:INDEX:L4_GPIO_Table]
MOV$cc $mask, $mask, ROR $num
ASSERT $mask <> $tmp
ASSERT $regs <> $tmp
ASSERT $num <> $tmp ; no point using $tmp if the two are the same!
ASSERT $regs <> $num
MOV$cc $regs, $num, LSR #5
EOR$cc $tmp, $num, #31
ADD$cc $regs, sb, $regs, LSL #2
MOV$cc $mask, #&80000000
LDR$cc $regs, [$regs, #:INDEX:L4_GPIO_Table]
MOV$cc $mask, $mask, ROR $num
]
|
ASSERT $mask <> $tmp
ASSERT $regs <> $tmp
ASSERT $num <> $tmp ; no point using $tmp if the two are the same!
ASSERT $regs <> $num
MOV$cc $regs, $num, LSR #5
EOR$cc $tmp, $num, #31
ADD$cc $regs, sb, $regs, LSL #2
MOV$cc $mask, #&80000000
LDR$cc $regs, [$regs, #:INDEX:L4_GPIO_Table]
MOV$cc $mask, $mask, ROR $num
]
MEND
; Set pin for output
MACRO
GPIO_SetAsOutput $regs, $mask, $temp, $cc
ASSERT $regs <> $temp
ASSERT $mask <> $temp
LDR$cc $temp, [$regs, #GPIO_OE]
BIC$cc $temp, $temp, $mask
STR$cc $temp, [$regs, #GPIO_OE]
MEND
; Set pin for input
MACRO
GPIO_SetAsInput $regs, $mask, $temp, $cc
ASSERT $regs <> $temp
ASSERT $mask <> $temp
LDR$cc $temp, [$regs, #GPIO_OE]
ORR$cc $temp, $temp, $mask
STR$cc $temp, [$regs, #GPIO_OE]
MEND
; Set output to 0
MACRO
GPIO_SetOutput0 $regs, $mask, $cc
STR$cc $mask, [$regs, #GPIO_CLEARDATAOUT]
MEND
; Set output to 1
MACRO
GPIO_SetOutput1 $regs, $mask, $cc
STR$cc $mask, [$regs, #GPIO_SETDATAOUT]
MEND
; Set output 0/1
; In:
; $val = zero, or non-zero
MACRO
GPIO_SetOutput $val, $regs, $mask
TEQ $val, #0
STRNE $mask, [$regs, #GPIO_SETDATAOUT]
STREQ $mask, [$regs, #GPIO_CLEARDATAOUT]
MEND
; Get input value
; Out:
; $val = zero, or non-zero
MACRO
GPIO_GetInput $val, $regs, $mask, $cc
ASSERT $mask <> $val
LDR$cc $val, [$regs, #GPIO_DATAIN]
AND$cc $val, $val, $mask
MEND
; Get GPIO IRQ # (constant pin)
MACRO
GPIO_GetIRQC $irq, $pin, $cc
MOV$cc $irq, #($pin>>5) + GPIO1_IRQ_NO
MEND
; Get GPIO IRQ # (register pin)
MACRO
GPIO_GetIRQR $irq, $pin, $cc
MOV$cc $irq, $pin, LSR #5
ADD$cc $irq, $irq, #GPIO1_IRQ_NO
MEND
; Get GPIO IRQ # (as DCD)
; In:
; $shared = "shared" to set bit 31
MACRO
GPIO_GetIRQD $pin, $shared
MEND
; Set pin for output
MACRO
GPIO_SetAsOutput $regs, $mask, $temp, $cc
ASSERT $regs <> $temp
ASSERT $mask <> $temp
LDR$cc $temp, [$regs, #GPIO_OE]
BIC$cc $temp, $temp, $mask
STR$cc $temp, [$regs, #GPIO_OE]
MEND
; Set pin for input
MACRO
GPIO_SetAsInput $regs, $mask, $temp, $cc
ASSERT $regs <> $temp
ASSERT $mask <> $temp
LDR$cc $temp, [$regs, #GPIO_OE]
ORR$cc $temp, $temp, $mask
STR$cc $temp, [$regs, #GPIO_OE]
MEND
; Set output to 0
MACRO
GPIO_SetOutput0 $regs, $mask, $cc
STR$cc $mask, [$regs, #GPIO_CLEARDATAOUT]
MEND
; Set output to 1
MACRO
GPIO_SetOutput1 $regs, $mask, $cc
STR$cc $mask, [$regs, #GPIO_SETDATAOUT]
MEND
; Set output 0/1
; In:
; $val = zero, or non-zero
MACRO
GPIO_SetOutput $val, $regs, $mask
TEQ $val, #0
STRNE $mask, [$regs, #GPIO_SETDATAOUT]
STREQ $mask, [$regs, #GPIO_CLEARDATAOUT]
MEND
; Get input value
; Out:
; $val = zero, or non-zero
MACRO
GPIO_GetInput $val, $regs, $mask, $cc
ASSERT $mask <> $val
LDR$cc $val, [$regs, #GPIO_DATAIN]
AND$cc $val, $val, $mask
MEND
; Get GPIO IRQ # (constant pin)
MACRO
GPIO_GetIRQC $irq, $pin, $cc
MOV$cc $irq, #($pin>>5) + GPIO1_IRQ_NO
MEND
; Get GPIO IRQ # (register pin)
MACRO
GPIO_GetIRQR $irq, $pin, $cc
MOV$cc $irq, $pin, LSR #5
ADD$cc $irq, $irq, #GPIO1_IRQ_NO
MEND
; Get GPIO IRQ # (as DCD)
; In:
; $shared = "shared" to set bit 31
MACRO
GPIO_GetIRQD $pin, $shared