Commit 8ef181eb authored by Ben Avison's avatar Ben Avison
Browse files

Replaced header file for licensing reasons

Detail:
  omap4_reg.h taken from FreeBSD projects/armv6/sys/arm/ti/omap4, trimmed to
  only include interrupt definitions, then updated so that symbol names and
  comments match Table 17.2 of the OMAP4460 TRM (SWPU235F) more closely - now
  the symbol names only differ in the prefix, and the absence of "IRQ"
  mid-string.  This was then translated very literally into objasm syntax to
  create hdr.omap4_reg, and used in place of hdr.irqs44xx.
Admin:
  Builds OK

Version 0.22. Tagged as 'OMAP4-0_22'
parent df5f69cd
hdr/** gitlab-language=armasm linguist-language=armasm linguist-detectable=true
s/** gitlab-language=armasm linguist-language=armasm linguist-detectable=true
c/** gitlab-language=c linguist-language=c linguist-detectable=true
h/** gitlab-language=c linguist-language=c linguist-detectable=true
/* (0.21)
/* (0.22)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.21
#define Module_MajorVersion_CMHG 0.22
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 28 Sep 2013
#define Module_Date_CMHG 30 Oct 2013
#define Module_MajorVersion "0.21"
#define Module_Version 21
#define Module_MajorVersion "0.22"
#define Module_Version 22
#define Module_MinorVersion ""
#define Module_Date "28 Sep 2013"
#define Module_Date "30 Oct 2013"
#define Module_ApplicationDate "28-Sep-13"
#define Module_ApplicationDate "30-Oct-13"
#define Module_ComponentName "OMAP4"
#define Module_ComponentPath "castle/RiscOS/Sources/HAL/OMAP4"
#define Module_FullVersion "0.21"
#define Module_HelpVersion "0.21 (28 Sep 2013)"
#define Module_LibraryVersionInfo "0:21"
#define Module_FullVersion "0.22"
#define Module_HelpVersion "0.22 (30 Oct 2013)"
#define Module_LibraryVersionInfo "0:22"
/*-
* Copyright (c) 2011
* Ben Gray <ben.r.gray@gmail.com>.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef OMAP4_REG_H_
#define OMAP4_REG_H_
/*
* Interrupt Controller Unit.
*
* Refer to the omap4_intr.c file for interrupt controller (GIC)
* implementation.
*
* Note:
* - 16 Interprocessor interrupts (IPI): ID[15:0]
* - 2 private Timer/Watchdog interrupts: ID[30:29]
* - 2 legacy nFIQ & nIRQ: one per CPU, bypasses the interrupt distributor
* logic and directly drives interrupt requests into CPU if used in
* legacy mode (else treated like other interrupts lines with ID28
* and ID31 respectively)
* - 128 hardware interrupts: ID[159:32] (rising-edge or high-level sensitive).
*/
#define OMAP44XX_HARDIRQ(x) (32 + (x))
#define OMAP44XX_IRQ_L2_CACHE OMAP44XX_HARDIRQ(0) /* L2 cache controller interrupt */
#define OMAP44XX_IRQ_CTI_0 OMAP44XX_HARDIRQ(1) /* Cross-trigger module 0 (CTI0) interrupt */
#define OMAP44XX_IRQ_CTI_1 OMAP44XX_HARDIRQ(2) /* Cross-trigger module 1 (CTI1) interrupt */
#define OMAP44XX_IRQ_RESERVED3 OMAP44XX_HARDIRQ(3) /* RESERVED */
#define OMAP44XX_IRQ_ELM OMAP44XX_HARDIRQ(4) /* Error location process completion */
#define OMAP44XX_IRQ_CMU_P OMAP44XX_HARDIRQ(5) /* Cache management unit interrupt */
#define OMAP44XX_IRQ_RESERVED6 OMAP44XX_HARDIRQ(6) /* RESERVED */
#define OMAP44XX_IRQ_SYS_N1 OMAP44XX_HARDIRQ(7) /* External interrupt 1 (active low) */
#define OMAP44XX_IRQ_RESERVED8 OMAP44XX_HARDIRQ(8) /* RESERVED */
#define OMAP44XX_IRQ_L3_DBG OMAP44XX_HARDIRQ(9) /* L3 interconnect debug error */
#define OMAP44XX_IRQ_L3_APP OMAP44XX_HARDIRQ(10) /* L3 interconnect application error */
#define OMAP44XX_IRQ_PRCM_MPU OMAP44XX_HARDIRQ(11) /* PRCM interrupt */
#define OMAP44XX_IRQ_SDMA_0 OMAP44XX_HARDIRQ(12) /* sDMA interrupt 0 */
#define OMAP44XX_IRQ_SDMA_1 OMAP44XX_HARDIRQ(13) /* sDMA interrupt 1 */
#define OMAP44XX_IRQ_SDMA_2 OMAP44XX_HARDIRQ(14) /* sDMA interrupt 2 */
#define OMAP44XX_IRQ_SDMA_3 OMAP44XX_HARDIRQ(15) /* sDMA interrupt 3 */
#define OMAP44XX_IRQ_MCBSP4 OMAP44XX_HARDIRQ(16) /* MCBSP4 interrupt */
#define OMAP44XX_IRQ_MCBSP1 OMAP44XX_HARDIRQ(17) /* MCBSP1 interrupt */
#define OMAP44XX_IRQ_SR_MPU OMAP44XX_HARDIRQ(18) /* SmartReflex MPU interrupt */
#define OMAP44XX_IRQ_SR_CORE OMAP44XX_HARDIRQ(19) /* SmartReflex Core interrupt */
#define OMAP44XX_IRQ_GPMC OMAP44XX_HARDIRQ(20) /* GPMC interrupt */
#define OMAP44XX_IRQ_SGX OMAP44XX_HARDIRQ(21) /* 2D/3D graphics module interrupt */
#define OMAP44XX_IRQ_MCBSP2 OMAP44XX_HARDIRQ(22) /* MCBSP2 interrupt */
#define OMAP44XX_IRQ_MCBSP3 OMAP44XX_HARDIRQ(23) /* MCBSP3 interrupt */
#define OMAP44XX_IRQ_ISS_5 OMAP44XX_HARDIRQ(24) /* Imaging subsystem interrupt 5 */
#define OMAP44XX_IRQ_DSS_DISPC OMAP44XX_HARDIRQ(25) /* Display controller interrupt */
#define OMAP44XX_IRQ_MAIL_U0_MPU OMAP44XX_HARDIRQ(26) /* Mailbox user 0 interrupt */
#define OMAP44XX_IRQ_C2C_SSCM_0 OMAP44XX_HARDIRQ(27) /* C2C status interrupt */
#define OMAP44XX_IRQ_DSP_MMU OMAP44XX_HARDIRQ(28) /* DSP MMU interrupt */
#define OMAP44XX_IRQ_GPIO1_MPU OMAP44XX_HARDIRQ(29) /* GPIO1 MPU interrupt */
#define OMAP44XX_IRQ_GPIO2_MPU OMAP44XX_HARDIRQ(30) /* GPIO2 MPU interrupt */
#define OMAP44XX_IRQ_GPIO3_MPU OMAP44XX_HARDIRQ(31) /* GPIO3 MPU interrupt */
#define OMAP44XX_IRQ_GPIO4_MPU OMAP44XX_HARDIRQ(32) /* GPIO4 MPU interrupt */
#define OMAP44XX_IRQ_GPIO5_MPU OMAP44XX_HARDIRQ(33) /* GPIO5 MPU interrupt */
#define OMAP44XX_IRQ_GPIO6_MPU OMAP44XX_HARDIRQ(34) /* GPIO6 MPU interrupt */
#define OMAP44XX_IRQ_RESERVED35 OMAP44XX_HARDIRQ(35) /* RESERVED */
#define OMAP44XX_IRQ_WDT3 OMAP44XX_HARDIRQ(36) /* WDTIMER3 overflow */
#define OMAP44XX_IRQ_GPT1 OMAP44XX_HARDIRQ(37) /* GPTIMER1 interrupt */
#define OMAP44XX_IRQ_GPT2 OMAP44XX_HARDIRQ(38) /* GPTIMER2 interrupt */
#define OMAP44XX_IRQ_GPT3 OMAP44XX_HARDIRQ(39) /* GPTIMER3 interrupt */
#define OMAP44XX_IRQ_GPT4 OMAP44XX_HARDIRQ(40) /* GPTIMER4 interrupt */
#define OMAP44XX_IRQ_GPT5 OMAP44XX_HARDIRQ(41) /* GPTIMER5 interrupt */
#define OMAP44XX_IRQ_GPT6 OMAP44XX_HARDIRQ(42) /* GPTIMER6 interrupt */
#define OMAP44XX_IRQ_GPT7 OMAP44XX_HARDIRQ(43) /* GPTIMER7 interrupt */
#define OMAP44XX_IRQ_GPT8 OMAP44XX_HARDIRQ(44) /* GPTIMER8 interrupt */
#define OMAP44XX_IRQ_GPT9 OMAP44XX_HARDIRQ(45) /* GPTIMER9 interrupt */
#define OMAP44XX_IRQ_GPT10 OMAP44XX_HARDIRQ(46) /* GPTIMER10 interrupt */
#define OMAP44XX_IRQ_GPT11 OMAP44XX_HARDIRQ(47) /* GPTIMER11 interrupt */
#define OMAP44XX_IRQ_MCSPI4 OMAP44XX_HARDIRQ(48) /* MCSPI4 interrupt */
#define OMAP44XX_IRQ_RESERVED49 OMAP44XX_HARDIRQ(49) /* RESERVED */
#define OMAP44XX_IRQ_RESERVED50 OMAP44XX_HARDIRQ(50) /* RESERVED */
#define OMAP44XX_IRQ_RESERVED51 OMAP44XX_HARDIRQ(51) /* RESERVED */
#define OMAP44XX_IRQ_RESERVED52 OMAP44XX_HARDIRQ(52) /* RESERVED */
#define OMAP44XX_IRQ_DSS_DSI1 OMAP44XX_HARDIRQ(53) /* Display Subsystem DSI1 interrupt */
#define OMAP44XX_IRQ_RESERVED54 OMAP44XX_HARDIRQ(54) /* RESERVED */
#define OMAP44XX_IRQ_RESERVED55 OMAP44XX_HARDIRQ(55) /* RESERVED */
#define OMAP44XX_IRQ_I2C1 OMAP44XX_HARDIRQ(56) /* I2C1 interrupt */
#define OMAP44XX_IRQ_I2C2 OMAP44XX_HARDIRQ(57) /* I2C2 interrupt */
#define OMAP44XX_IRQ_HDQ OMAP44XX_HARDIRQ(58) /* HDQ/1wire interrupt */
#define OMAP44XX_IRQ_MMC5 OMAP44XX_HARDIRQ(59) /* MMC5 interrupt */
#define OMAP44XX_IRQ_RESERVED60 OMAP44XX_HARDIRQ(60) /* RESERVED */
#define OMAP44XX_IRQ_I2C3 OMAP44XX_HARDIRQ(61) /* I2C3 interrupt */
#define OMAP44XX_IRQ_I2C4 OMAP44XX_HARDIRQ(62) /* I2C4 interrupt */
#define OMAP44XX_IRQ_RESERVED63 OMAP44XX_HARDIRQ(63) /* RESERVED */
#define OMAP44XX_IRQ_RESERVED64 OMAP44XX_HARDIRQ(64) /* RESERVED */
#define OMAP44XX_IRQ_MCSPI1 OMAP44XX_HARDIRQ(65) /* MCSPI1 interrupt */
#define OMAP44XX_IRQ_MCSPI2 OMAP44XX_HARDIRQ(66) /* MCSPI2 interrupt */
#define OMAP44XX_IRQ_HSI_P1_MPU OMAP44XX_HARDIRQ(67) /* HSI Port 1 interrupt */
#define OMAP44XX_IRQ_HSI_P2_MPU OMAP44XX_HARDIRQ(68) /* HSI Port 2 interrupt */
#define OMAP44XX_IRQ_FDIF_3 OMAP44XX_HARDIRQ(69) /* Face detect interrupt 3 */
#define OMAP44XX_IRQ_UART4 OMAP44XX_HARDIRQ(70) /* UART module 4 interrupt */
#define OMAP44XX_IRQ_HSI_DMA_MPU OMAP44XX_HARDIRQ(71) /* HSI DMA engine MPU request */
#define OMAP44XX_IRQ_UART1 OMAP44XX_HARDIRQ(72) /* UART1 interrupt */
#define OMAP44XX_IRQ_UART2 OMAP44XX_HARDIRQ(73) /* UART2 interrupt */
#define OMAP44XX_IRQ_UART3 OMAP44XX_HARDIRQ(74) /* UART3 interrupt */
#define OMAP44XX_IRQ_PBIAS OMAP44XX_HARDIRQ(75) /* Merged interrupt for PBIASlite1 and 2 */
#define OMAP44XX_IRQ_HSUSB_OHCI OMAP44XX_HARDIRQ(76) /* HSUSB MP host interrupt OHCI controller */
#define OMAP44XX_IRQ_HSUSB_EHCI OMAP44XX_HARDIRQ(77) /* HSUSB MP host interrupt EHCI controller */
#define OMAP44XX_IRQ_HSUSB_TLL OMAP44XX_HARDIRQ(78) /* HSUSB MP TLL interrupt */
#define OMAP44XX_IRQ_RESERVED79 OMAP44XX_HARDIRQ(79) /* RESERVED */
#define OMAP44XX_IRQ_WDT2 OMAP44XX_HARDIRQ(80) /* WDTIMER2 interrupt */
#define OMAP44XX_IRQ_RESERVED81 OMAP44XX_HARDIRQ(81) /* RESERVED */
#define OMAP44XX_IRQ_RESERVED82 OMAP44XX_HARDIRQ(82) /* RESERVED */
#define OMAP44XX_IRQ_MMC1 OMAP44XX_HARDIRQ(83) /* MMC1 interrupt */
#define OMAP44XX_IRQ_DSS_DSI2 OMAP44XX_HARDIRQ(84) /* Display subsystem DSI2 interrupt */
#define OMAP44XX_IRQ_RESERVED85 OMAP44XX_HARDIRQ(85) /* RESERVED */
#define OMAP44XX_IRQ_MMC2 OMAP44XX_HARDIRQ(86) /* MMC2 interrupt */
#define OMAP44XX_IRQ_MPU_ICR OMAP44XX_HARDIRQ(87) /* ICR interrupt */
#define OMAP44XX_IRQ_C2C_SSCM_1 OMAP44XX_HARDIRQ(88) /* C2C GPI interrupt */
#define OMAP44XX_IRQ_FSUSB OMAP44XX_HARDIRQ(89) /* FS-USB - host controller Interrupt */
#define OMAP44XX_IRQ_FSUSB_SMI OMAP44XX_HARDIRQ(90) /* FS-USB - host controller SMI Interrupt */
#define OMAP44XX_IRQ_MCSPI3 OMAP44XX_HARDIRQ(91) /* MCSPI3 interrupt */
#define OMAP44XX_IRQ_HSUSB_OTG OMAP44XX_HARDIRQ(92) /* HSUSB OTG controller interrupt */
#define OMAP44XX_IRQ_HSUSB_OTG_DMA OMAP44XX_HARDIRQ(93) /* HSUSB OTG DMA interrupt */
#define OMAP44XX_IRQ_MMC3 OMAP44XX_HARDIRQ(94) /* MMC3 interrupt */
#define OMAP44XX_IRQ_RESERVED95 OMAP44XX_HARDIRQ(95) /* RESERVED */
#define OMAP44XX_IRQ_MMC4 OMAP44XX_HARDIRQ(96) /* MMC4 interrupt */
#define OMAP44XX_IRQ_SLIMBUS1 OMAP44XX_HARDIRQ(97) /* SLIMBUS1 interrupt */
#define OMAP44XX_IRQ_SLIMBUS2 OMAP44XX_HARDIRQ(98) /* SLIMBUS2 interrupt */
#define OMAP44XX_IRQ_ABE_MPU OMAP44XX_HARDIRQ(99) /* Audio back-end interrupt */
#define OMAP44XX_IRQ_CORTEXM3_MMU OMAP44XX_HARDIRQ(100) /* Cortex-M3 MMU interrupt */
#define OMAP44XX_IRQ_DSS_HDMI OMAP44XX_HARDIRQ(101) /* Display subsystem HDMI interrupt */
#define OMAP44XX_IRQ_SR_IVA OMAP44XX_HARDIRQ(102) /* SmartReflex IVA interrupt */
#define OMAP44XX_IRQ_IVAHD_2 OMAP44XX_HARDIRQ(103) /* Sync interrupt from ICONT2 (vDMA) */
#define OMAP44XX_IRQ_IVAHD_1 OMAP44XX_HARDIRQ(104) /* Sync interrupt from ICONT1 */
#define OMAP44XX_IRQ_RESERVED105 OMAP44XX_HARDIRQ(105) /* RESERVED */
#define OMAP44XX_IRQ_RESERVED106 OMAP44XX_HARDIRQ(106) /* RESERVED */
#define OMAP44XX_IRQ_IVAHD_MAILBOX_0 OMAP44XX_HARDIRQ(107) /* IVAHD mailbox interrupt 0 */
#define OMAP44XX_IRQ_RESERVED108 OMAP44XX_HARDIRQ(108) /* RESERVED */
#define OMAP44XX_IRQ_MCASP1_AXINT OMAP44XX_HARDIRQ(109) /* McASP1 transmit interrupt */
#define OMAP44XX_IRQ_EMIF1 OMAP44XX_HARDIRQ(110) /* EMIF1 interrupt */
#define OMAP44XX_IRQ_EMIF2 OMAP44XX_HARDIRQ(111) /* EMIF2 interrupt */
#define OMAP44XX_IRQ_MCPDM OMAP44XX_HARDIRQ(112) /* MCPDM interrupt */
#define OMAP44XX_IRQ_DMM OMAP44XX_HARDIRQ(113) /* DMM interrupt */
#define OMAP44XX_IRQ_DMIC OMAP44XX_HARDIRQ(114) /* DMIC interrupt */
#define OMAP44XX_IRQ_RESERVED115 OMAP44XX_HARDIRQ(115) /* RESERVED */
#define OMAP44XX_IRQ_RESERVED116 OMAP44XX_HARDIRQ(116) /* RESERVED */
#define OMAP44XX_IRQ_RESERVED117 OMAP44XX_HARDIRQ(117) /* RESERVED */
#define OMAP44XX_IRQ_RESERVED118 OMAP44XX_HARDIRQ(118) /* RESERVED */
#define OMAP44XX_IRQ_SYS_N2 OMAP44XX_HARDIRQ(119) /* External interrupt 2 (active low) */
#define OMAP44XX_IRQ_KBD_CTL OMAP44XX_HARDIRQ(120) /* Keyboard controller interrupt */
#define OMAP44XX_IRQ_RESERVED121 OMAP44XX_HARDIRQ(121) /* RESERVED */
#define OMAP44XX_IRQ_RESERVED122 OMAP44XX_HARDIRQ(122) /* RESERVED */
#define OMAP44XX_IRQ_RESERVED123 OMAP44XX_HARDIRQ(123) /* RESERVED */
#define OMAP44XX_IRQ_RESERVED124 OMAP44XX_HARDIRQ(124) /* RESERVED */
#define OMAP44XX_IRQ_RESERVED125 OMAP44XX_HARDIRQ(125) /* RESERVED */
#define OMAP44XX_IRQ_THERMAL_ALERT OMAP44XX_HARDIRQ(126) /* General CORE Control Module thermal sensor alert interrupt */
#define OMAP44XX_IRQ_RESERVED127 OMAP44XX_HARDIRQ(127) /* RESERVED */
#endif /* OMAP4_REG_H_ */
......@@ -16,7 +16,7 @@
[ :LNOT: :DEF: __HAL_AUDIO_HDR__
GBLL __HAL_AUDIO_HDR__
GET hdr.irqs44xx
GET hdr.omap4_reg
GET hdr.SDMA
GET Hdr:AudioDevice
......
......@@ -16,7 +16,7 @@
[ :LNOT: :DEF: __HAL_GPIO_HDR__
GBLL __HAL_GPIO_HDR__
GET hdr.irqs44xx
GET hdr.omap4_reg
; GPIO registers - relative to L4_GPIO1, L4_GPIO2, L4_GPIO3, etc.
......@@ -68,7 +68,7 @@ GPIO_RISINGDETECT_FLAG * 4
GPIO_FALLINGDETECT_FLAG * 8
; interrupt number of lowest GPIO port
GPIO1_IRQ_NO * OMAP44XX_IRQ_GPIO1
GPIO1_IRQ_NO * OMAP44XX_IRQ_GPIO1_MPU
......
......@@ -16,7 +16,7 @@
[ :LNOT: :DEF: __HAL_I2C_HDR__
GBLL __HAL_I2C_HDR__
GET hdr.irqs44xx
GET hdr.omap4_reg
; I2C registers - relative to L4_I2C1, L4_I2C2, etc.
I2C_REVNB_LO * &00
......
......@@ -16,7 +16,7 @@
[ :LNOT: :DEF: __HAL_INTERRUPTS_HDR__
GBLL __HAL_INTERRUPTS_HDR__
GET hdr.irqs44xx
GET hdr.omap4_reg
; offsets of register in GIC Processor Interface (relative to MPU_GIC_PI)
GIC_CPU_CTRL * &000 ; CPU Interface Control Register (ICCICR)
......@@ -65,7 +65,7 @@ ICDICTR_SECUR_EXTN * ( 1 << 10) ; Security Extension implemented
ICDICTR_LSPI * (31 << 11) ; number of lockable SPI
INTERRUPT_MAX * (128 + OMAP44XX_IRQ_GIC_START) ; 128 interrupt lines
INTERRUPT_MAX OMAP44XX_HARDIRQ 128 ; 128 interrupt lines
] ; __HAL_INTERRUPTS_HDR__
......
......@@ -16,7 +16,7 @@
[ :LNOT: :DEF: __HAL_SDMA_HDR__
GBLL __HAL_SDMA_HDR__
GET hdr.irqs44xx
GET hdr.omap4_reg
GET hdr:DMADevice
......
......@@ -17,7 +17,7 @@
GBLL __HAL_SR44X_HDR__
GET Hdr:CPUClkDevice
GET hdr.irqs44xx
GET hdr.omap4_reg
; SmartReflex registers - relative to L4_SR_MPU,L4_SR_IVA,L4_SR_CORE
......
......@@ -16,7 +16,7 @@
[ :LNOT: :DEF: __HAL_TIMERS_HDR__
GBLL __HAL_TIMERS_HDR__
GET hdr.irqs44xx
GET hdr.omap4_reg
TIMER_MAX * 4 ; GPTIMER5-8.
; Other timers could be supported, but these 4 are in consecutive memory locations, making
......
......@@ -17,7 +17,7 @@
[ :LNOT: :DEF: __HAL_UART_HDR__
GBLL __HAL_UART_HDR__
GET hdr.irqs44xx
GET hdr.omap4_reg
UART_THR * &000 ; Transmit Holding Register
UART_RHR * &000 ; Receiver Holding Register
......
......@@ -16,7 +16,7 @@
[ :LNOT: :DEF: __HAL_VIDEO_HDR__
GBLL __HAL_VIDEO_HDR__
GET hdr.irqs44xx
GET hdr.omap4_reg
GET hdr:VideoDevice
......
; Copyright 2011 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;/*
; * OMAP4 Interrupt lines definitions
; *
; * Copyright (C) 2009-2010 Texas Instruments, Inc.
; *
; * Santosh Shilimkar (santosh.shilimkar@ti.com)
; * Benoit Cousson (b-cousson@ti.com)
; *
; * This file is automatically generated from the OMAP hardware databases.
; * We respectfully ask that any modifications to this file be coordinated
; * with the public linux-omap@vger.kernel.org mailing list and the
; * authors above to ensure that the autogeneration scripts are kept
; * up-to-date with the file contents.
; *
; * This program is free software; you can redistribute it and/or modify
; * it under the terms of the GNU General Public License version 2 as
; * published by the Free Software Foundation.
; */
[ :LNOT: :DEF: __HAL_IRQS44XX_HDR__
GBLL __HAL_IRQS44XX_HDR__
; OMAP44XX IRQs numbers definitions
; Cortex-A9 CPUn private interrupt IDs
; SGI (Software Generated Interrupts): 0 - 15
; PPI (Private Peripheral Interrupts): 16 - 31
OMAP44XX_IRQ_LOCALTIMER * 29
OMAP44XX_IRQ_LOCALWDT * 30
OMAP44XX_IRQ_GIC_START * 32
; SPI (Shared Peripheral Interrupts)
OMAP44XX_IRQ_PL310 * (0 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_CTI0 * (1 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_CTI1 * (2 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_ELM * (4 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_CMU * (5 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_SYS_1N * (7 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_L3_DBG * (9 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_L3_APP * (10 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_PRCM * (11 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_SDMA_0 * (12 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_SDMA_1 * (13 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_SDMA_2 * (14 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_SDMA_3 * (15 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_MCBSP4 * (16 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_MCBSP1 * (17 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_SR_MPU * (18 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_SR_CORE * (19 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_GPMC * (20 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_SGX * (21 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_MCBSP2 * (22 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_MCBSP3 * (23 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_ISS_5 * (24 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_DSS_DISPC * (25 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_MAIL_U0 * (26 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_C2C_SSCM_0 * (27 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_DSP_MMU * (28 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_GPIO1 * (29 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_GPIO2 * (30 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_GPIO3 * (31 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_GPIO4 * (32 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_GPIO5 * (33 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_GPIO6 * (34 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_WDT3 * (36 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_GPT1 * (37 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_GPT2 * (38 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_GPT3 * (39 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_GPT4 * (40 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_GPT5 * (41 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_GPT6 * (42 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_GPT7 * (43 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_GPT8 * (44 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_GPT9 * (45 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_GPT10 * (46 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_GPT11 * (47 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_MCSPI4 * (48 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_DSS_DSI1 * (53 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_I2C1 * (56 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_I2C2 * (57 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_HDQ * (58 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_MMC5 * (59 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_I2C3 * (61 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_I2C4 * (62 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_MCSPI1 * (65 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_MCSPI2 * (66 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_HSI_P1 * (67 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_HSI_P2 * (68 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_FDIF_3 * (69 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_UART4 * (70 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_HSI_DMA * (71 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_UART1 * (72 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_UART2 * (73 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_UART3 * (74 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_PBIAS * (75 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_HSUSB_OHCI * (76 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_HSUSB_EHCI * (77 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_HSUSB_TLL * (78 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_WDT2 * (80 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_MMC1 * (83 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_DSS_DSI2 * (84 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_MMC2 * (86 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_MPU_ICR * (87 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_C2C_SSCM_1 * (88 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_FSUSB * (89 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_FSUSB_SMI * (90 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_MCSPI3 * (91 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_HSUSB_OTG * (92 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_HSUSB_OTG_DMA * (93 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_MMC3 * (94 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_MMC4 * (96 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_SLIMBUS1 * (97 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_SLIMBUS2 * (98 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_ABE * (99 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_CORTEXM3_MMU * (100 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_DSS_HDMI * (101 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_SR_IVA * (102 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_IVAHD_1 * (103 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_IVAHD_0 * (104 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_IVAHD_MAILBOX_0 * (107 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_MCASP1_AX * (109 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_EMIF1 * (110 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_EMIF2 * (111 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_MCPDM * (112 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_DMM * (113 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_DMIC * (114 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_SYS_2N * (119 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_KBD_CTL * (120 + OMAP44XX_IRQ_GIC_START)
OMAP44XX_IRQ_THERMAL_ALERT * (126 + OMAP44XX_IRQ_GIC_START)
] ; __HAL_IRQS44XX_HDR__
END
;
; Copyright (c) 2011
; Ben Gray <ben.r.gray@gmail.com>.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions
; are met:
; 1. Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; 2. Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
; OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
; HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
; OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
; SUCH DAMAGE.
;
[ :LNOT: :DEF: __HAL_OMAP4_REG_HDR__
GBLL __HAL_OMAP4_REG_HDR__
;
; Interrupt Controller Unit.
;
; Refer to the omap4_intr.c file for interrupt controller (GIC)
; implementation.
;
; Note:
; - 16 Interprocessor interrupts (IPI): ID[15:0]
; - 2 private Timer/Watchdog interrupts: ID[30:29]
; - 2 legacy nFIQ & nIRQ: one per CPU, bypasses the interrupt distributor
; logic and directly drives interrupt requests into CPU if used in
; legacy mode (else treated like other interrupts lines with ID28
; and ID31 respectively)
; - 128 hardware interrupts: ID[159:32] (rising-edge or high-level sensitive).
;
MACRO
$lab OMAP44XX_HARDIRQ $x
$lab * 32 + $x
MEND
OMAP44XX_IRQ_L2_CACHE OMAP44XX_HARDIRQ 0 ; L2 cache controller interrupt
OMAP44XX_IRQ_CTI_0 OMAP44XX_HARDIRQ 1 ; Cross-trigger module 0 (CTI0) interrupt
OMAP44XX_IRQ_CTI_1 OMAP44XX_HARDIRQ 2 ; Cross-trigger module 1 (CTI1) interrupt
OMAP44XX_IRQ_RESERVED3 OMAP44XX_HARDIRQ 3 ; RESERVED
OMAP44XX_IRQ_ELM OMAP44XX_HARDIRQ 4 ; Error location process completion
OMAP44XX_IRQ_CMU_P OMAP44XX_HARDIRQ 5 ; Cache management unit interrupt
OMAP44XX_IRQ_RESERVED6 OMAP44XX_HARDIRQ 6 ; RESERVED
OMAP44XX_IRQ_SYS_N1 OMAP44XX_HARDIRQ 7 ; External interrupt 1 (active low)
OMAP44XX_IRQ_RESERVED8 OMAP44XX_HARDIRQ 8 ; RESERVED
OMAP44XX_IRQ_L3_DBG OMAP44XX_HARDIRQ 9 ; L3 interconnect debug error
OMAP44XX_IRQ_L3_APP OMAP44XX_HARDIRQ 10 ; L3 interconnect application error
OMAP44XX_IRQ_PRCM_MPU OMAP44XX_HARDIRQ 11 ; PRCM interrupt
OMAP44XX_IRQ_SDMA_0 OMAP44XX_HARDIRQ 12 ; sDMA interrupt 0
OMAP44XX_IRQ_SDMA_1 OMAP44XX_HARDIRQ 13 ; sDMA interrupt 1
OMAP44XX_IRQ_SDMA_2 OMAP44XX_HARDIRQ 14 ; sDMA interrupt 2
OMAP44XX_IRQ_SDMA_3 OMAP44XX_HARDIRQ 15 ; sDMA interrupt 3
OMAP44XX_IRQ_MCBSP4 OMAP44XX_HARDIRQ 16 ; MCBSP4 interrupt
OMAP44XX_IRQ_MCBSP1 OMAP44XX_HARDIRQ 17 ; MCBSP1 interrupt
OMAP44XX_IRQ_SR_MPU OMAP44XX_HARDIRQ 18 ; SmartReflex MPU interrupt
OMAP44XX_IRQ_SR_CORE OMAP44XX_HARDIRQ 19 ; SmartReflex Core interrupt
OMAP44XX_IRQ_GPMC OMAP44XX_HARDIRQ 20 ; GPMC interrupt
OMAP44XX_IRQ_SGX OMAP44XX_HARDIRQ 21 ; 2D/3D graphics module interrupt
OMAP44XX_IRQ_MCBSP2 OMAP44XX_HARDIRQ 22 ; MCBSP2 interrupt
OMAP44XX_IRQ_MCBSP3 OMAP44XX_HARDIRQ 23 ; MCBSP3 interrupt
OMAP44XX_IRQ_ISS_5 OMAP44XX_HARDIRQ 24 ; Imaging subsystem interrupt 5
OMAP44XX_IRQ_DSS_DISPC OMAP44XX_HARDIRQ 25 ; Display controller interrupt
OMAP44XX_IRQ_MAIL_U0_MPU OMAP44XX_HARDIRQ 26 ; Mailbox user 0 interrupt
OMAP44XX_IRQ_C2C_SSCM_0 OMAP44XX_HARDIRQ 27 ; C2C status interrupt
OMAP44XX_IRQ_DSP_MMU OMAP44XX_HARDIRQ 28 ; DSP MMU interrupt
OMAP44XX_IRQ_GPIO1_MPU OMAP44XX_HARDIRQ 29 ; GPIO1 MPU interrupt
OMAP44XX_IRQ_GPIO2_MPU OMAP44XX_HARDIRQ 30 ; GPIO2 MPU interrupt
OMAP44XX_IRQ_GPIO3_MPU OMAP44XX_HARDIRQ 31 ; GPIO3 MPU interrupt
OMAP44XX_IRQ_GPIO4_MPU OMAP44XX_HARDIRQ 32 ; GPIO4 MPU interrupt
OMAP44XX_IRQ_GPIO5_MPU OMAP44XX_HARDIRQ 33 ; GPIO5 MPU interrupt
OMAP44XX_IRQ_GPIO6_MPU OMAP44XX_HARDIRQ 34 ; GPIO6 MPU interrupt
OMAP44XX_IRQ_RESERVED35 OMAP44XX_HARDIRQ 35 ; RESERVED
OMAP44XX_IRQ_WDT3 OMAP44XX_HARDIRQ 36 ; WDTIMER3 overflow
OMAP44XX_IRQ_GPT1 OMAP44XX_HARDIRQ 37 ; GPTIMER1 interrupt
OMAP44XX_IRQ_GPT2 OMAP44XX_HARDIRQ 38 ; GPTIMER2 interrupt
OMAP44XX_IRQ_GPT3 OMAP44XX_HARDIRQ 39 ; GPTIMER3 interrupt
OMAP44XX_IRQ_GPT4 OMAP44XX_HARDIRQ 40 ; GPTIMER4 interrupt
OMAP44XX_IRQ_GPT5 OMAP44XX_HARDIRQ 41 ; GPTIMER5 interrupt
OMAP44XX_IRQ_GPT6 OMAP44XX_HARDIRQ 42 ; GPTIMER6 interrupt
OMAP44XX_IRQ_GPT7 OMAP44XX_HARDIRQ 43 ; GPTIMER7 interrupt
OMAP44XX_IRQ_GPT8 OMAP44XX_HARDIRQ 44 ; GPTIMER8 interrupt
OMAP44XX_IRQ_GPT9 OMAP44XX_HARDIRQ 45 ; GPTIMER9 interrupt
OMAP44XX_IRQ_GPT10 OMAP44XX_HARDIRQ 46 ; GPTIMER10 interrupt
OMAP44XX_IRQ_GPT11 OMAP44XX_HARDIRQ 47 ; GPTIMER11 interrupt
OMAP44XX_IRQ_MCSPI4 OMAP44XX_HARDIRQ 48 ; MCSPI4 interrupt
OMAP44XX_IRQ_RESERVED49 OMAP44XX_HARDIRQ 49 ; RESERVED
OMAP44XX_IRQ_RESERVED50 OMAP44XX_HARDIRQ 50 ; RESERVED
OMAP44XX_IRQ_RESERVED51 OMAP44XX_HARDIRQ 51 ; RESERVED
OMAP44XX_IRQ_RESERVED52 OMAP44XX_HARDIRQ 52 ; RESERVED
OMAP44XX_IRQ_DSS_DSI1 OMAP44XX_HARDIRQ 53 ; Display Subsystem DSI1 interrupt
OMAP44XX_IRQ_RESERVED54 OMAP44XX_HARDIRQ 54 ; RESERVED
OMAP44XX_IRQ_RESERVED55 OMAP44XX_HARDIRQ 55 ; RESERVED
OMAP44XX_IRQ_I2C1 OMAP44XX_HARDIRQ 56 ; I2C1 interrupt
OMAP44XX_IRQ_I2C2 OMAP44XX_HARDIRQ 57 ; I2C2 interrupt
OMAP44XX_IRQ_HDQ OMAP44XX_HARDIRQ 58 ; HDQ/1wire interrupt
OMAP44XX_IRQ_MMC5 OMAP44XX_HARDIRQ 59 ; MMC5 interrupt
OMAP44XX_IRQ_RESERVED60 OMAP44XX_HARDIRQ 60 ; RESERVED
OMAP44XX_IRQ_I2C3 OMAP44XX_HARDIRQ 61 ; I2C3 interrupt
OMAP44XX_IRQ_I2C4 OMAP44XX_HARDIRQ 62 ; I2C4 interrupt
OMAP44XX_IRQ_RESERVED63 OMAP44XX_HARDIRQ 63 ; RESERVED
OMAP44XX_IRQ_RESERVED64 OMAP44XX_HARDIRQ 64 ; RESERVED
OMAP44XX_IRQ_MCSPI1 OMAP44XX_HARDIRQ 65 ; MCSPI1 interrupt
OMAP44XX_IRQ_MCSPI2 OMAP44XX_HARDIRQ 66 ; MCSPI2 interrupt
OMAP44XX_IRQ_HSI_P1_MPU OMAP44XX_HARDIRQ 67 ; HSI Port 1 interrupt
OMAP44XX_IRQ_HSI_P2_MPU OMAP44XX_HARDIRQ 68 ; HSI Port 2 interrupt
OMAP44XX_IRQ_FDIF_3 OMAP44XX_HARDIRQ 69 ; Face detect interrupt 3
OMAP44XX_IRQ_UART4 OMAP44XX_HARDIRQ 70 ; UART module 4 interrupt
OMAP44XX_IRQ_HSI_DMA_MPU OMAP44XX_HARDIRQ 71 ; HSI DMA engine MPU request
OMAP44XX_IRQ_UART1 OMAP44XX_HARDIRQ 72 ; UART1 interrupt
OMAP44XX_IRQ_UART2 OMAP44XX_HARDIRQ 73 ; UART2 interrupt
OMAP44XX_IRQ_UART3 OMAP44XX_HARDIRQ 74 ; UART3 interrupt
OMAP44XX_IRQ_PBIAS OMAP44XX_HARDIRQ 75 ; Merged interrupt for PBIASlite1 and 2
OMAP44XX_IRQ_HSUSB_OHCI OMAP44XX_HARDIRQ 76 ; HSUSB MP host interrupt OHCI controller
OMAP44XX_IRQ_HSUSB_EHCI OMAP44XX_HARDIRQ 77 ; HSUSB MP host interrupt EHCI controller
OMAP44XX_IRQ_HSUSB_TLL OMAP44XX_HARDIRQ 78 ; HSUSB MP TLL interrupt
OMAP44XX_IRQ_RESERVED79 OMAP44XX_HARDIRQ 79 ; RESERVED
OMAP44XX_IRQ_WDT2 OMAP44XX_HARDIRQ 80 ; WDTIMER2 interrupt
OMAP44XX_IRQ_RESERVED81 OMAP44XX_HARDIRQ 81 ; RESERVED
OMAP44XX_IRQ_RESERVED82 OMAP44XX_HARDIRQ 82 ; RESERVED
OMAP44XX_IRQ_MMC1 OMAP44XX_HARDIRQ 83 ; MMC1 interrupt
OMAP44XX_IRQ_DSS_DSI2 OMAP44XX_HARDIRQ 84 ; Display subsystem DSI2 interrupt
OMAP44XX_IRQ_RESERVED85 OMAP44XX_HARDIRQ 85 ; RESERVED
OMAP44XX_IRQ_MMC2 OMAP44XX_HARDIRQ 86 ; MMC2 interrupt
OMAP44XX_IRQ_MPU_ICR OMAP44XX_HARDIRQ 87 ; ICR interrupt
OMAP44XX_IRQ_C2C_SSCM_1 OMAP44XX_HARDIRQ 88 ; C2C GPI interrupt
OMAP44XX_IRQ_FSUSB OMAP44XX_HARDIRQ 89 ; FS-USB - host controller Interrupt
OMAP44XX_IRQ_FSUSB_SMI OMAP44XX_HARDIRQ 90 ; FS-USB - host controller SMI Interrupt
OMAP44XX_IRQ_MCSPI3 OMAP44XX_HARDIRQ 91 ; MCSPI3 interrupt
OMAP44XX_IRQ_HSUSB_OTG OMAP44XX_HARDIRQ 92 ; HSUSB OTG controller interrupt
OMAP44XX_IRQ_HSUSB_OTG_DMA OMAP44XX_HARDIRQ 93 ; HSUSB OTG DMA interrupt
OMAP44XX_IRQ_MMC3 OMAP44XX_HARDIRQ 94 ; MMC3 interrupt
OMAP44XX_IRQ_RESERVED95 OMAP44XX_HARDIRQ 95 ; RESERVED
OMAP44XX_IRQ_MMC4 OMAP44XX_HARDIRQ 96 ; MMC4 interrupt
OMAP44XX_IRQ_SLIMBUS1 OMAP44XX_HARDIRQ 97 ; SLIMBUS1 interrupt
OMAP44XX_IRQ_SLIMBUS2 OMAP44XX_HARDIRQ 98 ; SLIMBUS2 interrupt
OMAP44XX_IRQ_ABE_MPU OMAP44XX_HARDIRQ 99 ; Audio back-end interrupt
OMAP44XX_IRQ_CORTEXM3_MMU OMAP44XX_HARDIRQ 100 ; Cortex-M3 MMU interrupt