Minor additions to OMAP4 HAL

Detail:
  s.board: adjusted max pixel-clock rate
  s.Top: changed to match rev 1.15 of HAL.OMAP3.s.Top
Admin:
  Updates from Willi Theiss

Version 0.02. Tagged as 'OMAP4-0_02'

VersionNum

-/* (0.01)
+/* (0.02)
  *
  * This file is automatically maintained by srccommit, do not edit manually.
  * Last processed by srccommit version: 1.1.
  *
  */
-#define Module_MajorVersion_CMHG        0.01
+#define Module_MajorVersion_CMHG        0.02
 #define Module_MinorVersion_CMHG        
-#define Module_Date_CMHG                12 Sep 2011
+#define Module_Date_CMHG                19 Oct 2011
 
-#define Module_MajorVersion             "0.01"
-#define Module_Version                  1
+#define Module_MajorVersion             "0.02"
+#define Module_Version                  2
 #define Module_MinorVersion             ""
-#define Module_Date                     "12 Sep 2011"
+#define Module_Date                     "19 Oct 2011"
 
-#define Module_ApplicationDate          "12-Sep-11"
+#define Module_ApplicationDate          "19-Oct-11"
 
 #define Module_ComponentName            "OMAP4"
 #define Module_ComponentPath            "castle/RiscOS/Sources/HAL/OMAP4"
 
-#define Module_FullVersion              "0.01"
-#define Module_HelpVersion              "0.01 (12 Sep 2011)"
-#define Module_LibraryVersionInfo       "0:1"
+#define Module_FullVersion              "0.02"
+#define Module_HelpVersion              "0.02 (19 Oct 2011)"
+#define Module_LibraryVersionInfo       "0:2"

s/Top

@@ -135,92 +135,16 @@ restart
 	DebugChar a3,a4,48
 	MSR	CPSR_c, #F32_bit+I32_bit+SVC32_mode
 	DebugChar a3,a4,49
-	; Invalidate L1 I/D
-	MOV	a1, #0			; set up for MCR
-	MCR	p15, 0, a1, c8, c7, 0	; invalidate TLBs
-	DebugChar a3,a4,50
-	MCR	p15, 0, a1, c7, c5, 0	; invalidate icache
-	DebugChar a3,a4,51
-	MCR	p15, 0, a1, c7, c5, 6	; invalidate BP array
-;	myISB
-	DebugChar a3,a4,52
-
-	; disable MMU stuff and caches
-	MRC	p15, 0, a1, c1, c0, 0
-	BIC	a1, a1, #&00002000	; clear bit 13 (--V-)
-	BIC	a1, a1, #&00000007	; clear bits 2:0 (-CAM)
-	ORR	a1, a1, #&00000002	; set bit 1 (--A-) Align
-	ORR	a1, a1, #&00000400	; set bit 10 (-SW--) Enable SWP/SWPB instruction
-	ORR	a1, a1, #&00000800	; set bit 11 (Z---) BTB
-	ORR	a1, a1, #&00001000	; set bit 12 (I) I-cache
-	MCR	p15, 0, a1, c1, c0, 0	; MMU, caches etc off
-	myISB
-	DebugChar a3,a4,53
-
-	; Invalidate data caches. To do this we must query their sizes
-	; The register describes up to 8 cache levels, so to provide some future-proofing
-	; I might as well implement a full cache clean routine here
-	MRC	p15, 1, a1, c0, c0, 1 ; Cache level ID register
-	DebugChar a3,a4,54
-	BIC	a1, a1, #&FF000000 ; Discard unification/coherency bits
-	MOV	a2, #0 ; Current cache level
-20
-	DebugChar a3,a4,49
-	ANDS	a3, a1, #7 ; Get flags
-	BEQ	%FT10 ; Cache clean complete
-	MCR	p15, 2, a2, c0, c0, 0 ; Program cache size selection register
-	myISB
-	MRC	p15, 1, a3, c0, c0, 0 ; Get size info
-	AND	v1, a3, #&7 ; log2(Line size)-2
-	BIC	a3, a3, #&F0000007 ; Clear flags & line size
-	MOV	v2, a3, LSL #19 ; Number of ways-1 in upper 10 bits
-	MOV	v3, a3, LSR #13 ; Number of sets-1 in lower 15 bits
-	; Way number needs to be packed right up at the high end of the data word; shift it up
-	CLZ	a4, v2
-	MOV	v2, v2, LSL a4
-	; Set number needs to start at log2(Line size)+2
-	MOV	v3, v3, LSL #4 ; Start at bit 4
-	MOV	v3, v3, LSL v1 ; Start at log2(Line size)+2
-	; Now calculate the offset numbers we will use to increment sets & ways
-	BIC	v4, v2, v2, LSL #1 ; Way increment
-	BIC	v5, v3, v3, LSL #1 ; Set increment
-	; Now we can finally clean this cache!
-	ORR	a3, a2, v3 ; Current way (0), set (max), and level
-30
-	MCR	p15, 0, a3, c7, c6, 2 ; Invalidate
-	ADDS	a3, a3, v4 ; Increment way
-	BCC	%BT30 ; Overflow will occur once ways are enumerated
-	TST	a3, v3 ; Are set bits all zero?
-	SUBNE	a3, a3, v5 ; No, so decrement set and loop around again
-	BNE	%BT30
-	; This cache is now clean. Move on to the next level.
-	DebugChar a3,a4,50
-	ADD	a2, a2, #2
-	MOVS	a1, a1, LSR #3
-	BNE	%BT20
-10
-	myDSB
-	myISB
-	DebugChar a1,a2,51
 
 	ADRL	v1, HAL_Base + OSROM_HALSize	; v1 -> RISC OS image
 
 	LDR	v8, [v1, #OSHdr_Entries]
 	ADD	v8, v8, v1			; v8 -> RISC OS entry table
 
-	ARM_read_control a1
-	; We assume that ARMs with an I cache can have it enabled while the MMU is off.
-	[ :LNOT:CacheOff
-	ORR   a1, a1, #MMUC_I
-	]
-	ARM_write_control a1			; whoosh
-	myISB
-
-	; Keep a soft copy of the CR in a banked register (R13_und)
-	MSR	CPSR_c, #F32_bit+I32_bit+UND32_mode
-	MOV	sp, a1
-	; Switch into SVC32 mode (we may have been in SVC26 before).
-	MSR	CPSR_c, #F32_bit+I32_bit+SVC32_mode
+	; Ensure CPU is set up
+	MOV	a1, #0
+	CallOSM	OS_InitARM
+	DebugChar a3,a4,50
 
 	; Initialise RAM
 	BL	init_ram

s/board

@@ -131,6 +131,6 @@ BoardConfigTable
 BoardConfigTable_End
 
 	;		DSI_BPP DSI_LANES	ACBias_freq	LCDType	Flags	LCDTimings	Max_PixelRate
-VBC_DVI	LCDCONFIG	24,	3,		&28,		TFT,	0,	0,		103000
+VBC_DVI	LCDCONFIG	24,	3,		&28,		TFT,	0,	0,		170100
 
 	END