Commit 797812f8 authored by Jeffrey Lee's avatar Jeffrey Lee
Browse files

Add HAL device implementation for PL310 L2 cache controller

Detail:
  s/PL310 - Add basic HAL device for the PL310 cache controller. Reports the base address to the OS and handles basic cache initialisation.
  Makefile - Include PL310 code
  hdr/StaticWS - Allocate workspace for HAL device
  s/Boot - Remove L2 cache initialisation from HAL_Init. Register PL310 device during HAL_InitDevices.
Admin:
  Tested on rev A6 Pandaboard
  Requires Kernel-5_35-4_79_2_252


Version 0.41. Tagged as 'OMAP4-0_41'
parent 1fa73584
......@@ -17,7 +17,7 @@
COMPONENT = OMAP-4 HAL
TARGET = OMAP4
OBJS = Top Boot Interrupts Timers CLib CLibAsm Stubs UART Debug PRCM Video USB I2C RTC SDMA TPS Audio GPIO GPMC NVMemory KbdScan SDIO SR44x PowerCtrl
OBJS = Top Boot Interrupts Timers CLib CLibAsm Stubs UART Debug PRCM Video USB I2C RTC SDMA TPS Audio GPIO GPMC NVMemory KbdScan SDIO SR44x PowerCtrl PL310
USBDIR = <Lib$Dir>.USB
HDRS =
......
/* (0.40)
/* (0.41)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.40
#define Module_MajorVersion_CMHG 0.41
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 21 Dec 2014
#define Module_Date_CMHG 11 Jan 2015
#define Module_MajorVersion "0.40"
#define Module_Version 40
#define Module_MajorVersion "0.41"
#define Module_Version 41
#define Module_MinorVersion ""
#define Module_Date "21 Dec 2014"
#define Module_Date "11 Jan 2015"
#define Module_ApplicationDate "21-Dec-14"
#define Module_ApplicationDate "11-Jan-15"
#define Module_ComponentName "OMAP4"
#define Module_ComponentPath "castle/RiscOS/Sources/HAL/OMAP4"
#define Module_FullVersion "0.40"
#define Module_HelpVersion "0.40 (21 Dec 2014)"
#define Module_LibraryVersionInfo "0:40"
#define Module_FullVersion "0.41"
#define Module_HelpVersion "0.41 (11 Jan 2015)"
#define Module_LibraryVersionInfo "0:41"
......@@ -126,7 +126,7 @@ NVRAMWS # HALDeviceSize
RTCWS # RTCSize
SDIOWS # SDHCISize * MaxSDControllers
PL310Device # HALDeviceSize
; align on 16 byte boundary
# (((:INDEX:@)+15):AND::NOT:15)-(:INDEX:@)
......
......@@ -166,6 +166,7 @@ HALdescriptor DATA
IMPORT SDIO_InitDevices
IMPORT NVMemory_Init
IMPORT NVMemory_InitDevice
IMPORT PL310_InitDevice
EXPORT Board_InitDevices_None
EXPORT Board_InitDevices_Panda
......@@ -406,16 +407,6 @@ HAL_Init
BL SetUpOSEntries
; The PL320 L2CC control registers aren't writable from non secure modes on
; this particular Cortex-A9, so call the OMAP4 HLOS support function (see
; TRM 27.5.1) to get it enabled
Push "v4-v5, sb, v7-v8"
LDR ip, =0x102 ; write control register
MOV a1, #1 ; L2 cache enable
DSB SY
SMC #0
Pull "v4-v5, sb, v7-v8"
; Map in the main IO ranges (L3, L4) and then store the offsets to the components
; we're interested in
MOV a1, #0
......@@ -721,6 +712,7 @@ HAL_InitDevices
BL VideoDevice_Init
BL Audio_Init
BL PowerCtrl_Init
BL PL310_InitDevice
; Board-specific HAL devices
LDR pc, [sb, #BoardConfig_InitDevices]
Board_InitDevices_None
......
; Copyright 2015 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
GET Hdr:ListOpts
GET Hdr:Macros
GET Hdr:System
$GetIO
GET Hdr:OSEntries
GET Hdr:HALEntries
GET Hdr:HALDevice
GET hdr.omap4430
GET hdr.StaticWS
GET hdr.omap4_reg
EXPORT PL310_InitDevice
IMPORT memcpy
; Basic PL310 HAL device
AREA |Asm$$Code|, CODE, READONLY, PIC
PL310_InitDevice ROUT
Push "lr"
ADRL a1, PL310Device
ADR a2, PL310Template
MOV a3, #HALDeviceSize
BL memcpy
LDR a2, L4_Per_Log
LDR a3, =MPU_PL310-L4_Per
ADD a2, a2, a3
STR a2, [a1, #HALDevice_Address]
; Register the device
MOV a2, a1
MOV a1, #0
CallOS OS_AddDevice
; Leave the OS to decide when to enable it - it will need to be ready
; to start performing maintenance ops
Pull "pc"
PL310Template
DCW HALDeviceType_SysPeri + HALDeviceSysPeri_CacheC
DCW HALDeviceID_CacheC_PL310
DCD HALDeviceBus_Sys + HALDeviceSysBus_AXI
DCD 0 ; API version
DCD PL310Desc
DCD 0 ; Address - Filled in at runtime
% 12 ; Reserved
DCD PL310Activate
DCD PL310Deactivate
DCD PL310Reset
DCD PL310Sleep
DCD OMAP44XX_IRQ_L2_CACHE
DCD 0
% 8
ASSERT (.-PL310Template) = HALDeviceSize
PL310Desc
DCB "PL310 L2 cache controller", 0
ALIGN
PL310Activate
Push "v4-v5, sb, v7-v8, lr"
; The PL310 L2CC control registers aren't writable from non secure
; modes, so call the OMAP4 HLOS support function (see TRM 27.5.1) to
; get it enabled
LDR ip, =0x102 ; write control register
MOV a1, #1 ; L2 cache enable
DSB SY
SMC #0
MOV a1, #1
Pull "v4-v5, sb, v7-v8, pc"
PL310Deactivate
PL310Reset
; Deactivate & reset not implemented
MOV pc, lr
PL310Sleep
MOV a1, #0 ; Previously at full power
MOV pc, lr
END
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