Commit 72842215 authored by Robert Sprowson's avatar Robert Sprowson
Browse files

Switch out, rather than comment out, FIQ code

FIQ's aren't currently supported, but this is now controlled by the 'FIQ_Supported' switch.

Version 0.30. Tagged as 'OMAP4-0_30'
parent 6d2e5e8a
/* (0.29)
/* (0.30)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.29
#define Module_MajorVersion_CMHG 0.30
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 09 Mar 2014
#define Module_Date_CMHG 22 Mar 2014
#define Module_MajorVersion "0.29"
#define Module_Version 29
#define Module_MajorVersion "0.30"
#define Module_Version 30
#define Module_MinorVersion ""
#define Module_Date "09 Mar 2014"
#define Module_Date "22 Mar 2014"
#define Module_ApplicationDate "09-Mar-14"
#define Module_ApplicationDate "22-Mar-14"
#define Module_ComponentName "OMAP4"
#define Module_ComponentPath "castle/RiscOS/Sources/HAL/OMAP4"
#define Module_FullVersion "0.29"
#define Module_HelpVersion "0.29 (09 Mar 2014)"
#define Module_LibraryVersionInfo "0:29"
#define Module_FullVersion "0.30"
#define Module_HelpVersion "0.30 (22 Mar 2014)"
#define Module_LibraryVersionInfo "0:30"
......@@ -309,213 +309,236 @@ HAL_IRQStatus
;
; ToDo: do we have FIQs in Non-Secure environment GIC ???
; FIQ_Supported part contains register names from OMAP3 implementation;
; this needs updating for GICv1 naming conventions!
;
GBLL FIQ_Supported
FIQ_Supported SETL {FALSE}
HAL_FIQEnable
[ FIQ_Supported
CMP a1, #INTERRUPT_MAX
MOVHS a1, #0
MOVHS pc, lr
; Disable interrupts while we update the controller
MRS a4, CPSR
ORR a3, a4, #F32_bit+I32_bit
MSR CPSR_c, a3
; Set the interrupt type & priority, and then unmask it
MOV a2, #1 ; highest priority for all FIQs.
LDR a3, MPU_INTC_Log
ADD ip, a3, #INTCPS_ILR
ASSERT INTCPS_ILR_SIZE = 4
STR a2, [ip, a1, LSL #2]
AND a2, a1, #&1F ; Mask bit
MOV a1, a1, LSR #5 ; BITS index
ASSERT INTCPS_BITS_SIZE = 32
ADD ip, a3, a1, LSL #5
MOV a1, #1
MOV a2, a1, LSL a2
LDR a1, [ip, #INTCPS_BITS+INTCPS_BITS_MIR] ; Get old state
STR a2, [ip, #INTCPS_BITS+INTCPS_BITS_MIR_CLEAR] ; Write to clear reg to set new state
MSR CPSR_c, a4 ; Re-enable interrupts
MVN a1, a1 ; Invert so we get a mask of enabled interrupts
AND a1, a1, a2 ; Test if it was enabled or not
MOV pc, lr
|
MOV a1, #0
MOV pc, lr
; CMP a1, #INTERRUPT_MAX
; MOVHS a1, #0
; MOVHS pc, lr
; ; Disable interrupts while we update the controller
; MRS a4, CPSR
; ORR a3, a4, #F32_bit+I32_bit
; MSR CPSR_c, a3
; ; Set the interrupt type & priority, and then unmask it
; MOV a2, #1 ; highest priority for all FIQs.
; LDR a3, MPU_INTC_Log
; ADD ip, a3, #INTCPS_ILR
; ASSERT INTCPS_ILR_SIZE = 4
; STR a2, [ip, a1, LSL #2]
; AND a2, a1, #&1F ; Mask bit
; MOV a1, a1, LSR #5 ; BITS index
; ASSERT INTCPS_BITS_SIZE = 32
; ADD ip, a3, a1, LSL #5
; MOV a1, #1
; MOV a2, a1, LSL a2
; LDR a1, [ip, #INTCPS_BITS+INTCPS_BITS_MIR] ; Get old state
; STR a2, [ip, #INTCPS_BITS+INTCPS_BITS_MIR_CLEAR] ; Write to clear reg to set new state
; MSR CPSR_c, a4 ; Re-enable interrupts
; MVN a1, a1 ; Invert so we get a mask of enabled interrupts
; AND a1, a1, a2 ; Test if it was enabled or not
; MOV pc, lr
] ; FIQ_Supported
HAL_FIQDisable
[ FIQ_Supported
CMP a1, #INTERRUPT_MAX
MOVHS a1, #0
MOVHS pc, lr
Push "lr"
; Disable interrupts while we update the controller (not necessarily needed for disabling them?)
MRS a4, CPSR
ORR a3, a4, #F32_bit+I32_bit
MSR CPSR_c, a3
; Check if this is actually an FIQ
LDR a3, MPU_INTC_Log
ASSERT INTCPS_ILR_SIZE = 4
ADD a2, a3, a1, LSL #2
LDR a2, [a2, #INTCPS_ILR]
TST a2, #1
MOVEQ a1, #0 ; This is an IRQ, so don't disable it
MSREQ CPSR_c, a4
Pull "pc", EQ
; Now mask the interrupt
AND a2, a1, #&1F ; Mask bit
MOV lr, a1, LSR #5 ; BITS index
ASSERT INTCPS_BITS_SIZE = 32
ADD ip, a3, lr, LSL #5
MOV lr, #1
MOV a2, lr, LSL a2
LDR lr, [ip, #INTCPS_BITS+INTCPS_BITS_MIR] ; Get old state
STR a2, [ip, #INTCPS_BITS+INTCPS_BITS_MIR_SET] ; Mask the interrupt
; Check if we just disabled the active interrupt
LDR ip, [a3, #INTCPS_SIR_FIQ]
CMP ip, a1
MOVEQ ip, #2
STREQ ip, [a3, #INTCPS_CONTROL]
[ DebugInterrupts
MOVEQ ip, #-1
STREQ ip, LastInterrupt_FIQ
]
MSR CPSR_c, a4 ; Re-enable interrupts
BIC a1, a2, lr ; Clear the masked interrupts from a2 to get nonzero result if it was enabled
Pull "pc"
|
MOV a1, #0
MOV pc, lr
; CMP a1, #INTERRUPT_MAX
; MOVHS a1, #0
; MOVHS pc, lr
; Push "lr"
; ; Disable interrupts while we update the controller (not necessarily needed for disabling them?)
; MRS a4, CPSR
; ORR a3, a4, #F32_bit+I32_bit
; MSR CPSR_c, a3
; ; Check if this is actually an FIQ
; LDR a3, MPU_INTC_Log
; ASSERT INTCPS_ILR_SIZE = 4
; ADD a2, a3, a1, LSL #2
; LDR a2, [a2, #INTCPS_ILR]
; TST a2, #1
; MOVEQ a1, #0 ; This is an IRQ, so don't disable it
; MSREQ CPSR_c, a4
; Pull "pc", EQ
; ; Now mask the interrupt
; AND a2, a1, #&1F ; Mask bit
; MOV lr, a1, LSR #5 ; BITS index
; ASSERT INTCPS_BITS_SIZE = 32
; ADD ip, a3, lr, LSL #5
; MOV lr, #1
; MOV a2, lr, LSL a2
; LDR lr, [ip, #INTCPS_BITS+INTCPS_BITS_MIR] ; Get old state
; STR a2, [ip, #INTCPS_BITS+INTCPS_BITS_MIR_SET] ; Mask the interrupt
; ; Check if we just disabled the active interrupt
; LDR ip, [a3, #INTCPS_SIR_FIQ]
; CMP ip, a1
; MOVEQ ip, #2
; STREQ ip, [a3, #INTCPS_CONTROL]
; [ DebugInterrupts
; MOVEQ ip, #-1
; STREQ ip, LastInterrupt_FIQ
; ]
; MSR CPSR_c, a4 ; Re-enable interrupts
; BIC a1, a2, lr ; Clear the masked interrupts from a2 to get nonzero result if it was enabled
; Pull "pc"
] ; FIQ_Supported
HAL_FIQDisableAll
[ FIQ_Supported
; This isn't particularly great, we need to scan the entire ILR array
; and work out which are FIQs, and then write to the ISR_SET registers
; We should probably keep our own array of enabled FIQs so this can be
; done more quickly
; MRS a4, CPSR
; ORR a3, a4, #F32_bit+I32_bit
; MSR CPSR_c, a3
; LDR a1, MPU_INTC_Log
; ADD a1, a1, #INTCPS_ILR
; MOV a2, #1 ; Mask to write
; ADD a3, a1, #INTCPS_BITS+INTCPS_BITS_MIR_SET-INTCPS_ILR
;HAL_FIQDisableAll_Loop1
; LDR ip, [a1],#INTCPS_ILR_SIZE
; TST ip, #1 ; 1=FIQ, 0=IRQ
; STRNE a2, [a3] ; Disable it
; MOVS a2, a2, LSL #1
; BCC HAL_FIQDisableAll_Loop1
; ; Move on to next word
; MOV a2, #1
; ADD a3, a3, #INTCPS_BITS_SIZE
;HAL_FIQDisableAll_Loop2
; LDR ip, [a1],#INTCPS_ILR_SIZE
; TST ip, #1 ; 1=FIQ, 0=IRQ
; STRNE a2, [a3] ; Disable it
; MOVS a2, a2, LSL #1
; BCC HAL_FIQDisableAll_Loop2
; ; Move on to last word
; MOV a2, #1
; ADD a3, a3, #INTCPS_BITS_SIZE
;HAL_FIQDisableAll_Loop3
; LDR ip, [a1],#INTCPS_ILR_SIZE
; TST ip, #1 ; 1=FIQ, 0=IRQ
; STRNE a2, [a3] ; Disable it
; MOVS a2, a2, LSL #1
; BCC HAL_FIQDisableAll_Loop3
; ; Done
; ASSERT INTCPS_BITS_COUNT = 3
; MSR CPSR_c, a4
; ; FIQDisableAll is only called during emergency situations, so restart INTC priority sorting to avoid having to rewrite various bits of RISC OS code to query FIQ sources and call FIQClear on each one (which would otherwise be the only legal way of stopping all FIQs from firing)
; LDR a2, MPU_INTC_Log
; MOV a1, #2
; STR a1, [a2, #INTCPS_CONTROL]
; ; Data synchronisation barrier to make sure INTC gets the message
; DSB SY
; [ DebugInterrupts
; MOV a1, #-1
; STR a1, LastInterrupt_FIQ
; ]
MRS a4, CPSR
ORR a3, a4, #F32_bit+I32_bit
MSR CPSR_c, a3
LDR a1, MPU_INTC_Log
ADD a1, a1, #INTCPS_ILR
MOV a2, #1 ; Mask to write
ADD a3, a1, #INTCPS_BITS+INTCPS_BITS_MIR_SET-INTCPS_ILR
HAL_FIQDisableAll_Loop1
LDR ip, [a1],#INTCPS_ILR_SIZE
TST ip, #1 ; 1=FIQ, 0=IRQ
STRNE a2, [a3] ; Disable it
MOVS a2, a2, LSL #1
BCC HAL_FIQDisableAll_Loop1
; Move on to next word
MOV a2, #1
ADD a3, a3, #INTCPS_BITS_SIZE
HAL_FIQDisableAll_Loop2
LDR ip, [a1],#INTCPS_ILR_SIZE
TST ip, #1 ; 1=FIQ, 0=IRQ
STRNE a2, [a3] ; Disable it
MOVS a2, a2, LSL #1
BCC HAL_FIQDisableAll_Loop2
; Move on to last word
MOV a2, #1
ADD a3, a3, #INTCPS_BITS_SIZE
HAL_FIQDisableAll_Loop3
LDR ip, [a1],#INTCPS_ILR_SIZE
TST ip, #1 ; 1=FIQ, 0=IRQ
STRNE a2, [a3] ; Disable it
MOVS a2, a2, LSL #1
BCC HAL_FIQDisableAll_Loop3
; Done
ASSERT INTCPS_BITS_COUNT = 3
MSR CPSR_c, a4
; FIQDisableAll is only called during emergency situations, so restart INTC priority
; sorting to avoid having to rewrite various bits of RISC OS code to query FIQ sources
; and call FIQClear on each one (which would otherwise be the only legal way of
; stopping all FIQs from firing)
LDR a2, MPU_INTC_Log
MOV a1, #2
STR a1, [a2, #INTCPS_CONTROL]
; Data synchronisation barrier to make sure INTC gets the message
DSB SY
[ DebugInterrupts
MOV a1, #-1
STR a1, LastInterrupt_FIQ
]
] ; FIQ_Supported
MOV pc, lr
HAL_FIQClear
; ; Restart INTC priority sorting
; LDR a2, MPU_INTC_Log
; MOV a1, #2
; STR a1, [a2, #INTCPS_CONTROL]
; ; Data synchronisation barrier to make sure INTC gets the message
; DSB SY
; [ DebugInterrupts
; MOV a1, #-1
; STR a1, LastInterrupt_FIQ
; ]
[ FIQ_Supported
; Restart INTC priority sorting
LDR a2, MPU_INTC_Log
MOV a1, #2
STR a1, [a2, #INTCPS_CONTROL]
; Data synchronisation barrier to make sure INTC gets the message
DSB SY
[ DebugInterrupts
MOV a1, #-1
STR a1, LastInterrupt_FIQ
]
] ; FIQ_Supported
MOV pc, lr
HAL_FIQStatus
[ FIQ_Supported
; Test if FIQ is firing, irrespective of mask state
CMP a1, #INTERRUPT_MAX
MOVHS a1, #0
MOVHS pc, lr
; First we need to make sure this is an FIQ, not an IRQ?
MRS a4, CPSR
ORR a3, a4, #F32_bit+I32_bit
MSR CPSR_c, a3
LDR a2, MPU_INTC_Log
ASSERT INTCPS_ILR_SIZE = 4
ADD a3, a2, a1, LSL #2
LDR a3, [a3, #INTCPS_ILR]
TST a3, #1
MOVEQ a1, #0 ; This is an IRQ, so it can't fire for FIQ
MSREQ CPSR_c, a4
MOVEQ pc, lr
; Now check if it's firing
ASSERT INTCPS_BITS_SIZE = 32
MOV a3, a1, LSR #5
ADD a3, a2, a3, LSL #5
LDR a3, [a3, #INTCPS_BITS+INTCPS_BITS_ITR]
MSR CPSR_c, a4
AND a1, a1, #31
MOV a1, a3, LSR a1 ; Shift and invert so 1=active
AND a1, a1, #1 ; 0 = not firing, 1 = firing
MOV pc, lr
|
MOV a1, #0
MOV pc, lr
; ; Test if FIQ is firing, irrespective of mask state
; CMP a1, #INTERRUPT_MAX
; MOVHS a1, #0
; MOVHS pc, lr
; ; First we need to make sure this is an FIQ, not an IRQ?
; MRS a4, CPSR
; ORR a3, a4, #F32_bit+I32_bit
; MSR CPSR_c, a3
; LDR a2, MPU_INTC_Log
; ASSERT INTCPS_ILR_SIZE = 4
; ADD a3, a2, a1, LSL #2
; LDR a3, [a3, #INTCPS_ILR]
; TST a3, #1
; MOVEQ a1, #0 ; This is an IRQ, so it can't fire for FIQ
; MSREQ CPSR_c, a4
; MOVEQ pc, lr
; ; Now check if it's firing
; ASSERT INTCPS_BITS_SIZE = 32
; MOV a3, a1, LSR #5
; ADD a3, a2, a3, LSL #5
; LDR a3, [a3, #INTCPS_BITS+INTCPS_BITS_ITR]
; MSR CPSR_c, a4
; AND a1, a1, #31
; MOV a1, a3, LSR a1 ; Shift and invert so 1=active
; AND a1, a1, #1 ; 0 = not firing, 1 = firing
; MOV pc, lr
] ; FIQ_Supported
HAL_FIQSource
[ FIQ_Supported
[ DebugInterrupts
LDR a1, LastInterrupt_FIQ
CMP a1, #0
BLT %FT10
Push "lr"
BL DebugHALPrint
= "HAL_FIQSource: Previous FIQ not cleared: ", 0
DebugReg a1
Pull "lr"
10
]
; Does the ARM think an interrupt is occuring?
MRC p15, 0, a1, c12, c1, 0
TST a1, #F32_bit
MOVEQ a1, #-1
[ DebugInterrupts
STREQ a1, LastInterrupt_FIQ
]
MOVEQ pc, lr
LDR a2, MPU_INTC_Log
LDR a1, [a2, #INTCPS_SIR_FIQ]
CMP a1, #INTERRUPT_MAX
ANDLO a1, a1, #&7F
[ DebugInterrupts
STRLO a1, LastInterrupt_FIQ
]
MOVLO pc, lr
; Authentic spurious interrupt - restart INTC and return -1
MOV a1, #-1
[ DebugInterrupts
STR a1, LastInterrupt_FIQ
]
MOV a3, #2
STR a3, [a2, #INTCPS_CONTROL]
; Data synchronisation barrier to make sure INTC gets the message
DSB SY
MOV pc, lr
|
MOV a1, #0
MOV pc, lr
; [ DebugInterrupts
; LDR a1, LastInterrupt_FIQ
; CMP a1, #0
; BLT %FT10
; Push "lr"
; BL DebugHALPrint
; = "HAL_FIQSource: Previous FIQ not cleared: ", 0
; DebugReg a1
; Pull "lr"
;10
; ]
; ; Does the ARM think an interrupt is occuring?
; MRC p15, 0, a1, c12, c1, 0
; TST a1, #F32_bit
; MOVEQ a1, #-1
; [ DebugInterrupts
; STREQ a1, LastInterrupt_FIQ
; ]
; MOVEQ pc, lr
; LDR a2, MPU_INTC_Log
; LDR a1, [a2, #INTCPS_SIR_FIQ]
; CMP a1, #INTERRUPT_MAX
; ANDLO a1, a1, #&7F
; [ DebugInterrupts
; STRLO a1, LastInterrupt_FIQ
; ]
; MOVLO pc, lr
; ; Authentic spurious interrupt - restart INTC and return -1
; MOV a1, #-1
; [ DebugInterrupts
; STR a1, LastInterrupt_FIQ
; ]
; MOV a3, #2
; STR a3, [a2, #INTCPS_CONTROL]
; ; Data synchronisation barrier to make sure INTC gets the message
; DSB SY
; MOV pc, lr
] ; FIQ_Supported
HAL_IRQMax
MOV a1, #INTERRUPT_MAX
......
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