Commit 6d2e5e8a authored by Robert Sprowson's avatar Robert Sprowson
Browse files

Rework of SDRAM detection

hdr.SDRC: Extra bit fields added to definitions
s.RAM: scan through all LISA_MAP register
       rework of clear loop (only one instance used)
s.Boot: scan through all LISA_MAP register

This should remove the dependence of the OMAP4 HAL to be run with a specific version of the accompanying loader.
Submission from Willi Theiss. Built, but not tested here,

Version 0.29. Tagged as 'OMAP4-0_29'
parent 71b85f75
/* (0.28)
/* (0.29)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.28
#define Module_MajorVersion_CMHG 0.29
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 08 Mar 2014
#define Module_Date_CMHG 09 Mar 2014
#define Module_MajorVersion "0.28"
#define Module_Version 28
#define Module_MajorVersion "0.29"
#define Module_Version 29
#define Module_MinorVersion ""
#define Module_Date "08 Mar 2014"
#define Module_Date "09 Mar 2014"
#define Module_ApplicationDate "08-Mar-14"
#define Module_ApplicationDate "09-Mar-14"
#define Module_ComponentName "OMAP4"
#define Module_ComponentPath "castle/RiscOS/Sources/HAL/OMAP4"
#define Module_FullVersion "0.28"
#define Module_HelpVersion "0.28 (08 Mar 2014)"
#define Module_LibraryVersionInfo "0:28"
#define Module_FullVersion "0.29"
#define Module_HelpVersion "0.29 (09 Mar 2014)"
#define Module_LibraryVersionInfo "0:29"
......@@ -139,8 +139,16 @@ DMM_LISA_MAP_i_SDRC_MAP_SDRC1 * ( 2 << 8) ; mapped on SDRC 1 only
DMM_LISA_MAP_i_SDRC_MAP_SDRC01 * ( 3 << 8) ; mapped on SDRC 0 + 1 (interleaved)
DMM_LISA_MAP_i_SDRC_ADDRSPC * ( 3 << 16) ; SDRAM controller address space
DMM_LISA_MAP_i_SDRC_ADDRSPC_SHIFT * 16
DMM_LISA_MAP_i_SDRC_ADDRSPC_SDRAM * ( 0 << 16) ; SDRAM on CS0 + CS1
DMM_LISA_MAP_i_SDRC_ADDRSPC_NVM * ( 1 << 16) ; NVM on CS1
DMM_LISA_MAP_i_SDRC_ADDRSPC_RES * ( 2 << 16) ; Reserved
DMM_LISA_MAP_i_SDRC_ADDRSPC_IR * ( 3 << 16) ; Internal Registers
DMM_LISA_MAP_i_SDRC_INTL * ( 3 << 18) ; SDRAM controller interleaving mode
DMM_LISA_MAP_i_SDRC_INTL_SHIFT * 18
DMM_LISA_MAP_i_SDRC_INTL_NONE * ( 0 << 18) ; No interleaving
DMM_LISA_MAP_i_SDRC_INTL_128B * ( 1 << 18) ; 128 Byte interleaving
DMM_LISA_MAP_i_SDRC_INTL_256B * ( 2 << 18) ; 256 Byte interleaving
DMM_LISA_MAP_i_SDRC_INTL_512B * ( 3 << 18) ; 512 Byte interleaving
DMM_LISA_MAP_i_SYS_SIZE * ( 7 << 20) ; DMM system section size
DMM_LISA_MAP_i_SYS_SIZE_SHIFT * 20
DMM_LISA_MAP_i_SYS_SIZE_16MB * ( 0 << 20)
......
......@@ -79,11 +79,27 @@ rom_checkedout_ok
LDR v1, =DMM_Base
MOV sp, #0
; Check LISA_MAP_0
LDR a3, [v1, #DMM_LISA_MAP_0]
; Check all DMM_LISA_MAP_i registers (starting with highest priority)
LDR a1, =DMM_LISA_MAP_3
LDR a4, =DMM_LISA_MAP_i_SDRC_ADDRSPC
05
LDR a2, =DMM_LISA_MAP_i_SDRC_MAP
LDR a3, [v1, a1]
ANDS a2, a3, a2 ; MAP_x used ?
BEQ no_cs0
BEQ %FT10
AND a2, a3, a4 ; check ADDRSPC
CMP a2, #DMM_LISA_MAP_i_SDRC_ADDRSPC_SDRAM
BEQ %FT15
10
; Next DMM_LISA_MAP_x
CMP a1, #DMM_LISA_MAP_0
SUBHI a1, a1, #4
BHI %BT05
; This should not happen: no RAM found
B .
15
; Check DMM_LISA_MAP_x
LDR a2, =DMM_LISA_MAP_i_SYS_SIZE
AND a2, a3, a2
MOV a2, a2, LSR #DMM_LISA_MAP_i_SYS_SIZE_SHIFT
......@@ -96,30 +112,9 @@ rom_checkedout_ok
MOV a1, #0
STR a1, [sp, #-4]!
CallOSM OS_AddRAM
DebugChar a3,a2,72
no_cs0
; Check LISA_MAP_1
LDR a3, [v1, #DMM_LISA_MAP_1]
LDR a2, =DMM_LISA_MAP_i_SDRC_MAP
ANDS a2, a3, a2 ; MAP_x used ?
BEQ no_cs1
LDR a2, =DMM_LISA_MAP_i_SYS_SIZE
AND a2, a3, a2
MOV a2, a2, LSR #DMM_LISA_MAP_i_SYS_SIZE_SHIFT
LDR a4, =(16 * 1024 * 1024) ; 16 MiB smallest size
MOV a4, a4, LSL a2 ; final size
AND a2, a3, #DMM_LISA_MAP_i_SYS_ADDR
ADD a3, a4, a2
LDR a4, =&FFFFFFFF
CMP sp, #0
ADDEQ sp, a2, #4096 ; If no CS0 set up stack in CS1
MOV a1, #0
STR a1, [sp, #-4]!
CallOSM OS_AddRAM
DebugChar v1,v2,71
no_cs1
DebugChar a3,a2,71
; check for reset cause: test PRM_RSTST.GLOBAL_COLD_RST
; Check for reset cause: test PRM_RSTST.GLOBAL_COLD_RST
LDR a3, =L4_PowerMan
ADD a3, a3, #DEVICE_PRM
LDR a2, [a3, #PRM_RSTST]
......
......@@ -12,9 +12,11 @@
; See the License for the specific language governing permissions and
; limitations under the License.
;
; Using the DMA controller to clear RAM is much faster than doing it with the CPU (with the cache/write buffer off, at least)
GBLL Use_DMA_Clear
Use_DMA_Clear SETL {TRUE}
; Using the DMA controller to clear RAM is much faster than doing it with the CPU
; (with the cache/write buffer off, at least)
GBLL Use_DMA_Clear
Use_DMA_Clear SETL {TRUE}
init_ram
; nothing to do here: MLO (x-loader) has already done it
......@@ -27,22 +29,29 @@ init_ram
; a1 <= Highest physical address in RAM +1
get_end_of_ram
LDR v1, =DMM_Base
; Check LISA_MAP_1
LDR a3, [v1, #DMM_LISA_MAP_1]
; check all DMM_LISA_MAP_i registers (starting with highest priority)
LDR a1, =DMM_LISA_MAP_3
LDR a4, =DMM_LISA_MAP_i_SDRC_ADDRSPC
05
LDR a2, =DMM_LISA_MAP_i_SDRC_MAP
LDR a3, [v1, a1]
ANDS a2, a3, a2 ; MAP_x used ?
BEQ %FT10
LDR a2, =DMM_LISA_MAP_i_SYS_SIZE
AND a2, a3, a2
MOV a2, a2, LSR #DMM_LISA_MAP_i_SYS_SIZE_SHIFT
LDR a4, =(16 * 1024 * 1024) ; 16 MiB smallest size
MOV a4, a4, LSL a2 ; final size
AND a2, a3, #DMM_LISA_MAP_i_SYS_ADDR
ADD a1, a4, a2
MOV pc, lr
AND a2, a3, a4 ; check ADDRSPC
CMP a2, #DMM_LISA_MAP_i_SDRC_ADDRSPC_SDRAM
BEQ %FT15
10
; No RAM in CS1; therefore must be in CS0
LDR a3, [v1, #DMM_LISA_MAP_0]
; next DMM_LISA_MAP_x
CMP a1, #DMM_LISA_MAP_0
SUBHI a1, a1, #4
BHI %BT05
; this should not happen: no RAM found
12
B %BT12
15
; check DMM_LISA_MAP_x
LDR a2, =DMM_LISA_MAP_i_SYS_SIZE
AND a2, a3, a2
MOV a2, a2, LSR #DMM_LISA_MAP_i_SYS_SIZE_SHIFT
......@@ -53,7 +62,6 @@ get_end_of_ram
MOV pc, lr
clear_ram
; Clear everything up to a1
; Can clobber all regs except v8 & sb
......@@ -92,10 +100,30 @@ clear_ram
]
MOV v2, a1
LDR v1, =DMM_Base
LDR a3, [v1, #DMM_LISA_MAP_0]
; check all DMM_LISA_MAP_i registers (starting with highest priority)
LDR a1, =DMM_LISA_MAP_3
LDR a4, =DMM_LISA_MAP_i_SDRC_ADDRSPC
05
LDR a2, =DMM_LISA_MAP_i_SDRC_MAP
LDR a3, [v1, a1]
ANDS a2, a3, a2 ; MAP_x used ?
BEQ %FT10
AND a2, a3, a4 ; check ADDRSPC
CMP a2, #DMM_LISA_MAP_i_SDRC_ADDRSPC_SDRAM
BEQ %FT15
10
; next DMM_LISA_MAP_x
CMP a1, #DMM_LISA_MAP_0
SUBHI a1, a1, #4
BHI %BT05
; this should not happen: no RAM found
12
B %BT12
15
; check DMM_LISA_MAP_x
LDR a2, =DMM_LISA_MAP_i_SYS_SIZE
AND a2, a3, a2
MOV a2, a2, LSR #DMM_LISA_MAP_i_SYS_SIZE_SHIFT
......@@ -106,7 +134,7 @@ clear_ram
CMP a1, a4
MOVGT a1, a4 ; Work out how much we're meant to be clearing
CMP a1, #0
BEQ %FT10
BEQ %FT30
[ Use_DMA_Clear
; To keep things simple we split the transfer into chunks small enough to fit inside
......@@ -160,77 +188,7 @@ clear_ram
SUBS a1, a1, #128
BGT %BT20
]
10
LDR v1, =DMM_Base
LDR a3, [v1, #DMM_LISA_MAP_1]
LDR a2, =DMM_LISA_MAP_i_SDRC_MAP
ANDS a2, a3, a2 ; MAP_x used ?
BEQ %FT30
LDR a2, =DMM_LISA_MAP_i_SYS_SIZE
AND a2, a3, a2
MOV a2, a2, LSR #DMM_LISA_MAP_i_SYS_SIZE_SHIFT
LDR a4, =(16 * 1024 * 1024) ; 16 MiB smallest size
MOV a4, a4, LSL a2 ; final size
AND a2, a3, #DMM_LISA_MAP_i_SYS_ADDR
SUB a1, v2, a2
CMP a1, a4
MOVGT a1, a4 ; Work out how much we're meant to be clearing
CMP a1, #0
BEQ %FT30
[ Use_DMA_Clear
; To keep things simple we split the transfer into chunks small enough to fit inside
; one frame (64MB) and wait for each one to complete
; This means we don't have to worry about the code breaking if the clear area isn't
; MB aligned (or 128 byte aligned, as the original code assumed)
MOV a1, a1, LSR #2 ; Number of elements remaining
MOV a3, #&1000000 ; Max elements per transfer+1 (not quite 64MB!)
40
LDR v1, [v5, #DMA4_CSRi]
STR v1, [v5, #DMA4_CSRi] ; Clear status register
CMP a1, a3
MOVLT v1, a1
SUBGE v1, a3, #1
STR v1, [v5, #DMA4_CENi]
SUB a1, a1, v1
STR a2, [v5, #DMA4_CDSAi]
ADD a2, a2, v1, LSL #2
LDR a4, =(DMA4_CCR_SEL_SRC_DST_SYNC + DMA4_CCR_CONST_FILL_ENABLE + DMA4_CCR_DST_AMODE_POST_INC + DMA4_CCR_ENABLE)
STR a4, [v5, #DMA4_CCRi] ; Enable channel
; Use the transfer size as a rough timer for how long we should wait
; before we start hammering the status register
50
SUBS v1, v1, #256
BGT %BT50
50
LDR v1, [v5, #DMA4_CSRi]
TST v1, #DMA4_CSR_LAST
BEQ %BT50
; Make doubly sure that it's finished by checking WR_ACTIVE/RD_ACTIVE
50
LDR v1, [v5, #DMA4_CCRi]
TST v1, #(DMA4_CCR_RD_ACTIVE + DMA4_CCR_WR_ACTIVE)
BNE %BT50
CMP a1, #0
BNE %BT40
|
MOV a3, #0
MOV a4, #0
MOV v1, #0
MOV v3, #0
MOV v4, #0
MOV v5, #0
MOV sp, #0
MOV ip, #0
40
STMIA a2!,{a3,a4,v1,v3,v4,v5,sp,ip} ; 32 bytes
STMIA a2!,{a3,a4,v1,v3,v4,v5,sp,ip} ; 64 bytes
STMIA a2!,{a3,a4,v1,v3,v4,v5,sp,ip} ; 96 bytes
STMIA a2!,{a3,a4,v1,v3,v4,v5,sp,ip} ; 128 bytes
SUBS a1, a1, #128
BGT %BT40
]
30
[ Use_DMA_Clear
; Invalidate the I-cache & BTC, just in case
......
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