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Commit 5052676f authored by Robert Sprowson's avatar Robert Sprowson
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Tidy ups to OMAP4 hdr.GPIO removed TWL/TPS pins (not available on... 

Tidy ups to OMAP4 hdr.GPIO removed TWL/TPS pins (not available on OMAP4/TWL6030) s.GPIO removed TWL/TPS related GPIO pins (not available on OMAP4/TWL6030) s.SDIO some code cleanup (remove OMAP3 specific stuff) s.Boot some code tweaks (tidy up)

Changes from Willi Theiss. Built, but not tested here.

Version 0.15. Tagged as 'OMAP4-0_15'
parent f8acd505
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Showing with 16 additions and 151 deletions
VersionNum
View file @ 5052676f
/* (0.14)
/* (0.15)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.14
#define Module_MajorVersion_CMHG 0.15
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 07 Apr 2013
#define Module_Date_CMHG 10 Apr 2013
#define Module_MajorVersion "0.14"
#define Module_Version 14
#define Module_MajorVersion "0.15"
#define Module_Version 15
#define Module_MinorVersion ""
#define Module_Date "07 Apr 2013"
#define Module_Date "10 Apr 2013"
#define Module_ApplicationDate "07-Apr-13"
#define Module_ApplicationDate "10-Apr-13"
#define Module_ComponentName "OMAP4"
#define Module_ComponentPath "castle/RiscOS/Sources/HAL/OMAP4"
#define Module_FullVersion "0.14"
#define Module_HelpVersion "0.14 (07 Apr 2013)"
#define Module_LibraryVersionInfo "0:14"
#define Module_FullVersion "0.15"
#define Module_HelpVersion "0.15 (10 Apr 2013)"
#define Module_LibraryVersionInfo "0:15"
hdr/GPIO
View file @ 5052676f
......@@ -71,39 +71,6 @@ GPIO_FALLINGDETECT_FLAG * 8
GPIO1_IRQ_NO * OMAP44XX_IRQ_GPIO1
; TWL/TPS GPIO registers
TPS_GPIODATAIN1 * &98 ; *3
TPS_GPIODATADIR1 * &9B ; *3
TPS_GPIODATAOUT1 * &9E ; *3
TPS_CLEARGPIODATAOUT1 * &A1 ; *3
TPS_SETGPIODATAOUT1 * &A4 ; *3
TPS_GPIO_DEBEN1 * &A7 ; *3
TPS_GPIO_CTRL * &AA
TPS_GPIOPUPCTR1 * &AB ; *5
TPS_GPIO_ISR1A * &B1 ; *3
TPS_GPIO_IMR1A * &B4 ; *3
TPS_GPIO_ISR1B * &B7 ; *3
TPS_GPIO_IMR1B * &BA ; *3
TPS_GPIO_EDR1 * &C0 ; *5
TPS_GPIO_SIH_CTRL * &C5
TPS_PMBR1 * &92
TPS_PMBR2 * &93
TPSGPIO_IIC * &49
TPS_GPIO_PIN_MAX * 17
; TWL/TPS LED registers
; (we treat these as extra output-only GPIOs, like Linux)
TPS_LEDEN * &EE
TPS_PWMAON * &EF
TPS_PWMAOFF * &F0
TPS_PWMBON * &F1
TPS_PWMBOFF * &F2
TPSLED_IIC * &4A
TPS_LED_PIN_MAX * 2
; OMAP GPIO related macros
; All assume sb = HAL workspace
......
s/Boot
View file @ 5052676f
......@@ -24,6 +24,7 @@
GET Hdr:Proc
GET Hdr:OSEntries
GET Hdr:HALEntries
GET Hdr:GPIODevice
GET hdr.omap4430
GET hdr.StaticWS
......@@ -755,9 +756,6 @@ HAL_InitDevices
Board_InitDevices_None
EXIT
GPIOType_OMAP4_Panda * 0
GPIORevision_Panda * 0
GPIORevision_PandaES * 1
Board_InitDevices_Panda
; SD needs boardtype and revision to configure the devices correctly
......
s/GPIO
View file @ 5052676f
......@@ -34,8 +34,6 @@
EXPORT GPIOx_SetAsOutput
EXPORT GPIOx_SetOutput
EXPORT GPIOx_SetAndEnableIRQ
IMPORT TPSRead
IMPORT TPSWrite
IMPORT IIC_DoOp_Poll
IMPORT DebugHALPrint
IMPORT DebugHALPrintReg
......@@ -52,104 +50,26 @@ GPIO_Init
BNE %BT10
MOV pc, lr
; a1 = GPIO # (OMAP or TPS or TPS LED)
; a1 = GPIO # (OMAP)
; a2 = initial value (zero or nonzero)
GPIOx_SetAsOutput
SUBS a3, a1, #GPIO_PIN_MAX
BGE %FT10
MOVGE pc, lr
; OMAP GPIO
GPIO_PrepareR a3, a4, a1
GPIO_SetAsOutput a3, a4, a1
GPIO_SetOutput a2, a3, a4
MOV pc, lr
10 ; TPS GPIO
Entry "v1-v3", 4
CMP a3, #TPS_GPIO_PIN_MAX
BGE %FT20
MOV a4, a3, LSR #3 ; Register offset
MOV v2, a2
AND a3, a3, #&7
MOV v3, #1
MOV v3, v3, LSL a3 ; Mask value
; If HAL_Init isn't done yet, we can't use OS_IICOpV
LDR v1, HALInitialised
CMP v1, #0
ADREQL v1, IIC_DoOp_Poll
LDRNE v1, OSentries+4*OS_IICOpV
MOV a1, #TPSGPIO_IIC*2
MOV a2, sp
MOV a3, #1
ADD a4, a4, #TPS_GPIODATADIR1
BL TPSRead
; TODO - Handle error!
LDRB ip, [a2]
ORR ip, ip, v3
STRB ip, [a2]
MOV a1, #TPSGPIO_IIC*2
BL TPSWrite
STRB v3, [a2]
MOV a1, #TPSGPIO_IIC*2
CMP v2, #0
ADDNE a4, a4, #TPS_SETGPIODATAOUT1-TPS_GPIODATADIR1
ADDEQ a4, a4, #TPS_CLEARGPIODATAOUT1-TPS_GPIODATADIR1
BL TPSWrite
EXIT
20 ; TPS LED
; Match the behaviour of Linux:
; a2=0 sets the LED*ON and LED*PWM bits
; a2!=0 clears them
MOVEQ v3, #&55 ; Mask for LEDA bits
MOVNE v3, #&AA ; Mask for LEDB bits
CMP a2, #0
MOVNE v2, #0 ; a2!=0, don't set any bits
ANDEQ v2, v3, #&33 ; a2=0, set appropriate LED*ON and LED*PWM bit
MOV a1, #TPSLED_IIC*2
MOV a2, sp
MOV a3, #1
MOV a4, #TPS_LEDEN
; If HAL_Init isn't done yet, we can't use OS_IICOpV
LDR v1, HALInitialised
CMP v1, #0
ADREQL v1, IIC_DoOp_Poll
LDRNE v1, OSentries+4*OS_IICOpV
BL TPSRead
LDRB ip, [a2]
BIC ip, ip, v3
ORR ip, ip, v2
STRB ip, [a2]
MOV a1, #TPSLED_IIC*2
BL TPSWrite
EXIT
; a1 = GPIO # (OMAP or TPS)
; a1 = GPIO # (OMAP)
; a2 = value (zero or nonzero)
GPIOx_SetOutput
SUBS a3, a1, #GPIO_PIN_MAX
BGE %FT10
MOVGE pc, lr
; OMAP GPIO
GPIO_PrepareR a3, a4, a1
GPIO_SetOutput a2, a3, a4
MOV pc, lr
10 ; TPS GPIO
Entry "v1-v2", 4
MOV a4, a3, LSR #3 ; Register offset
CMP a2, #0
AND a3, a3, #&7
ADDNE a4, a4, #TPS_SETGPIODATAOUT1
MOV v1, #1
ADDEQ a4, a4, #TPS_CLEARGPIODATAOUT1
MOV v1, v1, LSL a3 ; Mask value
MOV a2, sp
STRB v1, [sp]
MOV a1, #TPSGPIO_IIC*2
; If HAL_Init isn't done yet, we can't use OS_IICOpV
LDR v1, HALInitialised
CMP v1, #0
ADREQL v1, IIC_DoOp_Poll
LDRNE v1, OSentries+4*OS_IICOpV
MOV a3, #1
BL TPSWrite
EXIT
; a1 = GPIO # (OMAP only!)
; a2 = IRQ type flags:
......
s/SDIO
View file @ 5052676f
......@@ -37,6 +37,7 @@
GET Hdr:ListOpts
GET Hdr:Macros
GET Hdr:OSEntries
GET Hdr:GPIODevice
GET hdr.omap4430
GET hdr.GPIO
GET hdr.irqs44xx
......@@ -62,27 +63,6 @@ INIT_PROCEDURE_TIME * 1000 ; in us
; Frequency of the clock which we divide to produce SDCLK
FCLK_FREQ * 96000 ; in kHz
; differentiate between OMAP4460 (ES) and OMAP4430
GPIORevision_Panda * 0
GPIORevision_PandaES * 1
; Selected bits from PadConf registers (7.6.3 of spruf98b)
PADCONF_MASK * &FFFF
PADCONF_INPUTENABLE * 1 :SHL: 8
PADCONF_MUXMODE_GPIO * 4 :SHL: 0
; Bits within the PBIAS register (7.6.4.102 of spruf98b)
PBIASLITESUPPLYHIGH1 * 1 :SHL: 15
PBIASLITEVMODEEROR1 * 1 :SHL: 11
PBIASLITESPEEDCTRL1 * 1 :SHL: 10
PBIASLITEPWRDNZ1 * 1 :SHL: 9
PBIASLITEVMODE1 * 1 :SHL: 8
PBIASLITESUPPLYHIGH0 * 1 :SHL: 7
PBIASLITEVMODEEROR0 * 1 :SHL: 3
PBIASLITESPEEDCTRL0 * 1 :SHL: 2
PBIASLITEPWRDNZ0 * 1 :SHL: 1
PBIASLITEVMODE0 * 1 :SHL: 0
; RISC OS device numbers for each controller's IRQ line
MMC1_IRQ * OMAP44XX_IRQ_MMC1
......
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