Commit 4d183182 authored by Robert Sprowson's avatar Robert Sprowson
Browse files

Update to OMAP4 HAL.

OMAP4Dev.castle.RiscOS.Sources.HAL.OMAP4.hdr.Audio
    added further definitions for TWL6040 audio chip
    changes for working sound support
OMAP4Dev.castle.RiscOS.Sources.HAL.OMAP4.hdr.SDMA
    added further register descriptions according OMAP4 TRM
    changes for working sound support
OMAP4Dev.castle.RiscOS.Sources.HAL.OMAP4.hdr.UART
    added further register descriptions according OMAP4 TRM
OMAP4Dev.castle.RiscOS.Sources.HAL.OMAP4.hdr.omap4430
    added definitions for OMAP4460 (Panda ES)
OMAP4Dev.castle.RiscOS.Sources.HAL.OMAP4.s.board
    adjusted max pixel-clock rate
    order of UART entries changed
OMAP4Dev.castle.RiscOS.Sources.HAL.OMAP4.s.Boot
    don't reset debug UART
OMAP4Dev.castle.RiscOS.Sources.HAL.OMAP4.s.Top
    modifications according to OMAP3 version
OMAP4Dev.castle.RiscOS.Sources.HAL.OMAP4.s.debug
OMAP4Dev.castle.RiscOS.Sources.HAL.OMAP4.s.UART
    changes according to hdr.UART changes; HAL_UARTModemControl
OMAP4Dev.castle.RiscOS.Sources.HAL.OMAP4.s.RAM
    use definitions from hdr.SDMA
OMAP4Dev.castle.RiscOS.Sources.HAL.OMAP4.s.SDMA
    use definitions from hdr.SDMA
    changes for working sound support
OMAP4Dev.castle.RiscOS.Sources.HAL.OMAP4.s.Video
    added code to VideoDevice_Activate (enable DSS power)
OMAP4Dev.castle.RiscOS.Sources.HAL.OMAP4.hdr.omap4430
OMAP4Dev.castle.RiscOS.Sources.HAL.OMAP4.hdr.SDMA
OMAP4Dev.castle.RiscOS.Sources.HAL.OMAP4.s.Audio
OMAP4Dev.castle.RiscOS.Sources.HAL.OMAP4.s.SDMA
    changes for working sound support

Submissions from Willi Theiss. Compiles, but not tested here.

Version 0.05. Tagged as 'OMAP4-0_05'
parent 57fc88a7
......@@ -29,7 +29,6 @@ LNK_TARGET = custom
AIFDBG = aif._OMAP4
GPADBG = gpa.GPA
include StdRules
include StdTools
include CModule
......@@ -57,7 +56,7 @@ aof.${TARGET}: ${ROM_OBJS_} ${ROM_LIBS} ${DIRS} ${ROM_DEPEND}
linked.${TARGET}: aof.${TARGET}
${LD} ${LDFLAGS} ${LDLINKFLAGS} -o $@ -bin -base 0xFC000000 aof.${TARGET}
${AIFDBG}: ${ROM_OBJS_}
${AIFDBG}: ${ROM_OBJS_} ${ROM_LIBS}
${MKDIR} aif
${LD} -aif -bin -d -o ${AIFDBG} ${ROM_OBJS_} ${ROM_LIBS}
......
/* (0.04)
/* (0.05)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.04
#define Module_MajorVersion_CMHG 0.05
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 06 Dec 2011
#define Module_Date_CMHG 11 Feb 2012
#define Module_MajorVersion "0.04"
#define Module_Version 4
#define Module_MajorVersion "0.05"
#define Module_Version 5
#define Module_MinorVersion ""
#define Module_Date "06 Dec 2011"
#define Module_Date "11 Feb 2012"
#define Module_ApplicationDate "06-Dec-11"
#define Module_ApplicationDate "11-Feb-12"
#define Module_ComponentName "OMAP4"
#define Module_ComponentPath "castle/RiscOS/Sources/HAL/OMAP4"
#define Module_FullVersion "0.04"
#define Module_HelpVersion "0.04 (06 Dec 2011)"
#define Module_LibraryVersionInfo "0:4"
#define Module_FullVersion "0.05"
#define Module_HelpVersion "0.05 (11 Feb 2012)"
#define Module_LibraryVersionInfo "0:5"
......@@ -102,42 +102,42 @@ TWL6040_IIC * &4B
; TWL6040 register
TWL6040_REG_ASICID * 0x01
TWL6040_REG_ASICREV * 0x02
TWL6040_REG_INTID * 0x03
TWL6040_REG_INTMR * 0x04
TWL6040_REG_NCPCTL * 0x05
TWL6040_REG_LDOCTL * 0x06
TWL6040_REG_HPPLLCTL * 0x07
TWL6040_REG_LPPLLCTL * 0x08
TWL6040_REG_LPPLLDIV * 0x09
TWL6040_REG_AMICBCTL * 0x0A
TWL6040_REG_DMICBCTL * 0x0B
TWL6040_REG_MICLCTL * 0x0C
TWL6040_REG_MICRCTL * 0x0D
TWL6040_REG_MICGAIN * 0x0E
TWL6040_REG_LINEGAIN * 0x0F
TWL6040_REG_HSLCTL * 0x10
TWL6040_REG_HSRCTL * 0x11
TWL6040_REG_HSGAIN * 0x12
TWL6040_REG_EARCTL * 0x13
TWL6040_REG_HFLCTL * 0x14
TWL6040_REG_HFLGAIN * 0x15
TWL6040_REG_HFRCTL * 0x16
TWL6040_REG_HFRGAIN * 0x17
TWL6040_REG_VIBCTLL * 0x18
TWL6040_REG_VIBDATL * 0x19
TWL6040_REG_VIBCTLR * 0x1A
TWL6040_REG_VIBDATR * 0x1B
TWL6040_REG_HKCTL1 * 0x1C
TWL6040_REG_HKCTL2 * 0x1D
TWL6040_REG_GPOCTL * 0x1E
TWL6040_REG_ALB * 0x1F
TWL6040_REG_DLB * 0x20
TWL6040_REG_INTID * 0x03 ; Interrupt ID Register
TWL6040_REG_INTMR * 0x04 ; Interrupt Mask Register
TWL6040_REG_NCPCTL * 0x05 ; NCP Control
TWL6040_REG_LDOCTL * 0x06 ; LDO Control
TWL6040_REG_HPPLLCTL * 0x07 ; High Performance PLL Control
TWL6040_REG_LPPLLCTL * 0x08 ; Low Power PLL Control
TWL6040_REG_LPPLLDIV * 0x09 ; Low Power PLL Divider
TWL6040_REG_AMICBCTL * 0x0A ; Analog Microphone Biasing Control
TWL6040_REG_DMICBCTL * 0x0B ; Digital Microphone Biasing Control
TWL6040_REG_MICLCTL * 0x0C ; Microphone Left Channel Control
TWL6040_REG_MICRCTL * 0x0D ; Microphone Right Channel Control
TWL6040_REG_MICGAIN * 0x0E ; Microphone Amplifier Gain
TWL6040_REG_LINEGAIN * 0x0F ; Line Amplifier Gain
TWL6040_REG_HSLCTL * 0x10 ; Headset Left Channel Control
TWL6040_REG_HSRCTL * 0x11 ; Headset Right Channel Control
TWL6040_REG_HSGAIN * 0x12 ; Headset Left/Right Channel Gain
TWL6040_REG_EARCTL * 0x13 ; Ear Channel Control
TWL6040_REG_HFLCTL * 0x14 ; Hands-free Left Channel Control
TWL6040_REG_HFLGAIN * 0x15 ; Hands-free Left Channel Gain
TWL6040_REG_HFRCTL * 0x16 ; Hands-free Right Channel Control
TWL6040_REG_HFRGAIN * 0x17 ; Hands-free Right Channel Gain
TWL6040_REG_VIBCTLL * 0x18 ; Vibrator Left Channel Control
TWL6040_REG_VIBDATL * 0x19 ; Vibrator Left Channel Data
TWL6040_REG_VIBCTLR * 0x1A ; Vibrator Right Channel Control
TWL6040_REG_VIBDATR * 0x1B ; Vibrator Right Channel Data
TWL6040_REG_HKCTL1 * 0x1C ; Hook Detect Control 1
TWL6040_REG_HKCTL2 * 0x1D ; Hook Detect Control 2
TWL6040_REG_GPOCTL * 0x1E ; General Purpose Output Buffer Control
TWL6040_REG_ALB * 0x1F ; Analog Loop-Back
TWL6040_REG_DLB * 0x20 ; Digital Loop-Back
TWL6040_REG_TRIM1 * 0x28
TWL6040_REG_TRIM2 * 0x29
TWL6040_REG_TRIM3 * 0x2A
TWL6040_REG_HSOTRIM * 0x2B
TWL6040_REG_HFOTRIM * 0x2C
TWL6040_REG_ACCCTL * 0x2D
TWL6040_REG_HSOTRIM * 0x2B ; Headset Offset Trimming
TWL6040_REG_HFOTRIM * 0x2C ; Hands-free Offset Trimming
TWL6040_REG_ACCCTL * 0x2D ; Access Control
TWL6040_REG_STATUS * 0x2E
; INTID (0x03) fields
......@@ -155,11 +155,18 @@ TWL6040_ALLINT_MSK * 0x7B
; NCPCTL (0x05) fields
TWL6040_NCPENA * (1 << 0)
TWL6040_NCPMODE * (1 << 1)
TWL6040_NCPFETCTL * (1 << 2)
TWL6040_NCPFETSIZE * (7 << 3)
TWL6040_NCPOPEN * (1 << 6)
; LDOCTL (0x06) fields
TWL6040_LSLDOENA * (1 << 0)
TWL6040_LSLDOSLEEP * (1 << 1)
TWL6040_HSLDOENA * (1 << 2)
TWL6040_HSLDOSLEEP * (1 << 3)
TWL6040_LSLDOHZ * (1 << 4)
TWL6040_HSLDOHZ * (1 << 5)
TWL6040_REFENA * (1 << 6)
TWL6040_OSCENA * (1 << 7)
......@@ -182,29 +189,121 @@ TWL6040_LPLLSEL * (1 << 2)
TWL6040_LPLLFIN * (1 << 3)
TWL6040_HPLLSEL * (1 << 4)
; HSLCTL (0x10) fields
TWL6040_HSDACMODEL * (1 << 1)
TWL6040_HSDRVMODEL * (1 << 3)
; HSRCTL (0x11) fields
TWL6040_HSDACMODER * (1 << 1)
TWL6040_HSDRVMODER * (1 << 3)
; VIBCTLL (0x18) fields
TWL6040_VIBCTRLLN * (1 << 4)
TWL6040_VIBCTRLLP * (1 << 2)
TWL6040_VIBENAL * (1 << 0)
; VIBCTLL (0x19) fields
TWL6040_VIBCTRLRN * (1 << 4)
TWL6040_VIBCTRLRP * (1 << 2)
TWL6040_VIBENAR * (1 << 0)
; AMICBCTL (0x0A) fields
TWL6040_HMICBENA * (1 << 0)
TWL6040_HMICBSLP * (1 << 1)
TWL6040_HMICBPD * (1 << 2)
TWL6040_HMICBSCDIS * (1 << 3)
TWL6040_MMICBENA * (1 << 4)
TWL6040_MMICBSLP * (1 << 5)
TWL6040_MMICBPD * (1 << 6)
TWL6040_MMICBSCDIS * (1 << 7)
; DMICBCTL (0x0B) fields
TWL6040_DMICB1ENA * (1 << 0)
TWL6040_DMICB1SLP * (1 << 1)
TWL6040_DMICB1SEL * (1 << 2)
TWL6040_DMICB1SCDIS * (1 << 3)
TWL6040_DMICB2ENA * (1 << 4)
TWL6040_DMICB2SLP * (1 << 5)
TWL6040_DMICB2SEL * (1 << 6)
TWL6040_DMICB2SCDIS * (1 << 7)
; MICLCTL (0x0C) fields
TWL6040_MICAMPLENA * (1 << 0)
TWL6040_LINAMPLENA * (1 << 1)
TWL6040_ADCLENA * (1 << 2)
TWL6040_MICLSEL * (3 << 3)
TWL6040_MICLSEL_HS * (0 << 3)
TWL6040_MICLSEL_MAIN * (1 << 3)
TWL6040_MICLSEL_AUXFM * (2 << 3)
TWL6040_MICLSEL_NONE * (3 << 3)
; MICRCTL (0x0D) fields
TWL6040_MICAMPRENA * (1 << 0)
TWL6040_LINAMPRENA * (1 << 1)
TWL6040_ADCRENA * (1 << 2)
TWL6040_MICRSEL * (3 << 3)
TWL6040_MICRSEL_HS * (0 << 3)
TWL6040_MICRSEL_AUXMIC * (1 << 3)
TWL6040_MICRSEL_AUXFM * (2 << 3)
TWL6040_MICRSEL_NONE * (3 << 3)
; MICGAIN (0x0E) fields
TWL6040_MICGAINL * (7 << 0)
TWL6040_MICGAINR * (7 << 3)
TWL6040_MICATTL * (1 << 6)
TWL6040_MICATTR * (1 << 7)
; LINEGAIN (0x0F) fields
TWL6040_LINEGAINL * (7 << 0)
TWL6040_LINEGAINR * (7 << 3)
; HSLCTL (0x10) & HSRCTL (0x11) fields
TWL6040_HSDACENA * (1 << 0)
TWL6040_HSDACMODE * (1 << 1)
TWL6040_HSDRVENA * (1 << 2)
TWL6040_HSDRVMODE * (1 << 3)
TWL6040_HSDRVPD * (1 << 4)
TWL6040_HSDAC * (1 << 5)
TWL6040_HSFMLOOP * (1 << 6)
TWL6040_HSMN2ST * (1 << 7) ; only HSRCTL: Mono to Stereo
; HSGAIN (0x12) fields
TWL6040_HSGAINL * (15 << 0)
TWL6040_HSGAINR * (15 << 4)
; EARCTL (0x13) fields
TWL6040_EARENA * (1 << 0)
TWL6040_EARGAIN * (15 << 1)
TWL6040_SELEARFIR * (1 << 5)
; HFLCTL (0x14) & HFRCTL (0x16) fields
TWL6040_HFDACENA * (1 << 0)
TWL6040_HFPGAENA * (1 << 1)
TWL6040_HFDAC * (1 << 2)
TWL6040_HFFMLOOP * (1 << 3)
TWL6040_HFDRVENA * (1 << 4)
TWL6040_HFMN2ST * (1 << 5) ; only HFRCTL: Mono to Stereo
TWL6040_HFSWENA * (1 << 6)
; VIBCTLL (0x18) & VIBCTLR (0x1A) fields
TWL6040_VIBENA * (1 << 0)
TWL6040_VIBSEL * (1 << 1)
TWL6040_VIBCTRL * (1 << 2)
TWL6040_VIBCTRLP * (1 << 3)
TWL6040_VIBCTRLN * (1 << 4)
TWL6040_VIBLOOPDIS * (1 << 5)
; HSOTRIM (0x2B) fields
TWL6040_HSLO * (15 << 0)
TWL6040_HSRO * (15 << 4)
; HFOTRIM (0x2C) fields
TWL6040_HFLO * (15 << 0)
TWL6040_HFRO * (15 << 4)
; ACCCTL (0x2D) fields
TWL6040_I2CSEL * (1 << 0)
TWL6040_PDMI2CSEL * (1 << 1)
TWL6040_RESETSPLIT * (1 << 2)
TWL6040_INTCLRMODE * (1 << 3)
TWL6040_I2CMODE * (3 << 4)
TWL6040_I2CMODE_NM * (0 << 4) ; Normal Mode
TWL6040_I2CMODE_FM * (1 << 4) ; Fast Mode
TWL6040_I2CMODE_FMP * (2 << 4) ; Fast Mode Plus
TWL6040_I2CMODE_HS * (3 << 4) ; High Speed Mode
TWL6040_CLK32KSEL * (1 << 6)
; STATUS (0x2E) fields
TWL6040_HKCOMP * (1 << 0)
TWL6040_PLUGCOMP * (1 << 1)
TWL6040_HFLOCDET * (1 << 2) ; HFL Over Current Detection
TWL6040_HFROCDET * (1 << 3) ; HFR Over Current Detection
TWL6040_VIBLOCDET * (1 << 4) ; VIBL Over Current Detection
TWL6040_VIBROCDET * (1 << 5) ; VIBR Over Current Detection
TWL6040_TSHUTDET * (1 << 6) ; Thermal Detection Status
; McPDM DMA request IDs
......@@ -227,30 +326,31 @@ AudioDevice # HALDevice_Audio_Size_1
AudioRegs # 4 ; L4_McPDM_Log
AudioWorkspace # 4 ; HAL workspace pointer
AudioMode # 4 ; Softcopy of CODEC_MODE register
AudioChipCache # 48 ; Softcopy of Audio chip register
Audio_DeviceSize * :INDEX: @
; Mixer device
^ 0
MixerChannel_HeadsetOut # 1 ; Stereo headset output
MixerChannel_Predriver # 1 ; Stereo speaker predriver output
MixerChannel_Earphone # 1 ; Mono speaker output
MixerChannel_HandsFree # 1 ; Stereo hands-free output
MixerChannel_CarkitOut # 1 ; Stereo carkit output
MixerChannel_AuxOutput # 1 ; Stereo FM/aux output
MixerChannel_System # 1 ; Stereo sound data generated by computer
MixerChannel_HeadsetMic # 1 ; Mono headset mic
MixerChannel_HeadsetMic # 1 ; Stereo headset mic
MixerChannel_AuxInput # 1 ; Stereo FM/aux input
MixerChannel_CarkitMic # 1 ; Mono carkit mic
MixerChannel_MainMic # 1 ; Mono main mic
MixerChannels * :INDEX: @
^ 0, a1
; Public bits
MixerDevice # HALDevice_Mixer_Size
MixerDevice # HALDevice_Mixer_Size + 4 ; +4 for API 0.1
; Private bits
MixerSettings # 8 * MixerChannels
MixerHeadsetGain # 2 ; Cached HS_GAIN_SET value
MixerPredriverGain # 2 ; Cached PREDL_CTL, PREDR_CTL regs
MixerHandsFreeGain # 2 ; Cached HFL_CTL, HFR_CTL regs
MixerCarkitOutGain # 2 ; Cached PRECKL_CTL, PRECKR_CTL regs
MixerSystemGain # 2 ; Cached ARXL1PGA, ARXR1PGA regs
MixerHeadsetGain # 2 ; Cached HSGAIN value
MixerEarphoneGain # 2 ; Cached EARCTL reg
MixerHandsFreeGain # 2 ; Cached HFLCTL, HFRCTL regs
MixerAuxOutputGain # 2 ; Cached HFLCTL, HFRCTL regs
MixerSystemGain # 2 ; Cached LINEGAIN regs
MixerDisableFlags # 1 ; Copy of BoardConfig_MixerChans, for convenience
# 1 ; Spare
Mixer_DeviceSize * :INDEX: @
......
......@@ -606,10 +606,10 @@ C15 CN 15
DCI &F57FF04E ; DSB ST
|
[ "$option"="ISH"
DCI &F57FF04D ; DSB ISH
DCI &F57FF04B ; DSB ISH
|
[ "$option"="ISHST"
DCI &F57FF04C ; DSB ISHST
DCI &F57FF04A ; DSB ISHST
|
[ "$option"="NSH"
DCI &F57FF047 ; DSB NSH
......@@ -657,10 +657,10 @@ C15 CN 15
DCI &F57FF05E ; DMB ST
|
[ "$option"="ISH"
DCI &F57FF05D ; DMB ISH
DCI &F57FF05B ; DMB ISH
|
[ "$option"="ISHST"
DCI &F57FF05C ; DMB ISHST
DCI &F57FF05A ; DMB ISHST
|
[ "$option"="NSH"
DCI &F57FF057 ; DMB NSH
......
......@@ -41,30 +41,167 @@ DMA4_GCR * &078
DMA4_i * &080 ; Base of per-channel registers
; Per-channel registers:
DMA4_CCRi * &00
DMA4_CLNK_CTRLi * &04
DMA4_CICRi * &08
DMA4_CSRi * &0C
DMA4_CSDPi * &10
DMA4_CENi * &14
DMA4_CFNi * &18
DMA4_CSSAi * &1C
DMA4_CDSAi * &20
DMA4_CSEIi * &24
DMA4_CSFIi * &28
DMA4_CDEIi * &2C
DMA4_CDFIi * &30
DMA4_CSACi * &34
DMA4_CDACi * &38
DMA4_CCENi * &3C
DMA4_CCFNi * &40
DMA4_COLORi * &44
DMA4_CDPi * &50
DMA4_CNDPi * &54
DMA4_CCDNi * &58
DMA4_CCRi * &00 ; Channel Control Register
DMA4_CLNK_CTRLi * &04 ; Channel Link Control Register
DMA4_CICRi * &08 ; Channel Interrupt Control Register
DMA4_CSRi * &0C ; Channel Status Register
DMA4_CSDPi * &10 ; Channel Source Destination Parameters
DMA4_CENi * &14 ; Channel Element Number
DMA4_CFNi * &18 ; Channel Frame Number
DMA4_CSSAi * &1C ; Channel Source Start Address
DMA4_CDSAi * &20 ; Channel Destination Start Address
DMA4_CSEIi * &24 ; Channel Source Element Index
DMA4_CSFIi * &28 ; Channel Source Frame Index
DMA4_CDEIi * &2C ; Channel Destination Element Index
DMA4_CDFIi * &30 ; Channel Destination Frame Index
DMA4_CSACi * &34 ; Channel Source Address Counter
DMA4_CDACi * &38 ; Channel Destination Address Counter
DMA4_CCENi * &3C ; Channel Current Element Number
DMA4_CCFNi * &40 ; Channel Current Frame Number
DMA4_COLORi * &44 ; Channel Color Key
DMA4_CDPi * &50 ; Channel Descriptor Parameter
DMA4_CNDPi * &54 ; Channel Next Descriptor Pointer
DMA4_CCDNi * &58 ; Channel Current Descriptor Number
DMA4_CHANNEL_SIZE * &060 ; Size/stride of per-channel register blocks
; bits in DMA4_SYSSTATUS
DMA4_SYSSTATUS_RESETDONE * (1 << 0)
; bits in DMA4_OCP_SYSCONFIG
DMA4_OCP_SYSCONFIG_AUTOIDLE * (1 << 0)
DMA4_OCP_SYSCONFIG_SIDLEMODE * (3 << 3)
DMA4_OCP_SYSCONFIG_SIDLEMODE_FORCE * (0 << 3)
DMA4_OCP_SYSCONFIG_SIDLEMODE_NONE * (1 << 3)
DMA4_OCP_SYSCONFIG_SIDLEMODE_SMART * (2 << 3)
DMA4_OCP_SYSCONFIG_EMUFREE * (1 << 5)
DMA4_OCP_SYSCONFIG_CLOCKACTIVITY * (3 << 8)
DMA4_OCP_SYSCONFIG_MIDLEMODE * (3 << 12)
DMA4_OCP_SYSCONFIG_MIDLEMODE_FORCE * (0 << 12)
DMA4_OCP_SYSCONFIG_MIDLEMODE_NONE * (1 << 12)
DMA4_OCP_SYSCONFIG_MIDLEMODE_SMART * (2 << 12)
; bits in DMA4_GCR
DMA4_GCR_MAX_CHANNEL_FIFO_DEPTH * (255 << 0)
DMA4_GCR_HI_THREAD_RESERVED * ( 3 << 12)
DMA4_GCR_HI_LO_FIFO_BUDGET * ( 3 << 14)
DMA4_GCR_ARBITRAION_RATE * (255 << 16)
DMA4_GCR_ARBITRAION_RATE_SHIFT * 16
DMA4_GCR_CHANNEL_ID_GATE * (1 << 24)
; bits in Channel Control Register DMA4_CCRi
DMA4_CCR_SYNCHRO_CONTROL * (31 << 0)
DMA4_CCR_FS * (1 << 5)
DMA4_CCR_READ_PRIORITY * (1 << 6)
DMA4_CCR_ENABLE * (1 << 7)
DMA4_CCR_SUSPEND_SENSITIVE * (1 << 8)
DMA4_CCR_RD_ACTIVE * (1 << 9)
DMA4_CCR_WR_ACTIVE * (1 << 10)
DMA4_CCR_SRC_AMODE * (3 << 12)
DMA4_CCR_SRC_AMODE_CONST * (0 << 12) ; Constant Address Mode
DMA4_CCR_SRC_AMODE_POST_INC * (1 << 12) ; Post-Increment Address Mode
DMA4_CCR_SRC_AMODE_SINGLE_INDEX * (2 << 12) ; Single Index Address Mode
DMA4_CCR_SRC_AMODE_DOUBLE_INDEX * (3 << 12) ; Double Index Address Mode
DMA4_CCR_DST_AMODE * (3 << 14)
DMA4_CCR_DST_AMODE_CONST * (0 << 14) ; Constant Address Mode
DMA4_CCR_DST_AMODE_POST_INC * (1 << 14) ; Post-Increment Address Mode
DMA4_CCR_DST_AMODE_SINGLE_INDEX * (2 << 14) ; Single Index Address Mode
DMA4_CCR_DST_AMODE_DOUBLE_INDEX * (3 << 14) ; Double Index Address Mode
DMA4_CCR_CONST_FILL_ENABLE * (1 << 16)
DMA4_CCR_TRANSPARENT_COPY_ENABLE * (1 << 17)
DMA4_CCR_BS * (1 << 18)
DMA4_CCR_SYNCHRO_CONTROL_UPPER * (3 << 19)
DMA4_CCR_SYNCHRO_CONTROL_UPPER_SHIFT * 19
DMA4_CCR_SUPERVISOR * (1 << 22)
DMA4_CCR_PREFETCH * (1 << 23)
DMA4_CCR_SEL_SRC_DST_SYNC * (1 << 24)
DMA4_CCR_BUFFERING_DISABLE * (1 << 25)
DMA4_CCR_WRITE_PRIORITY * (1 << 26)
; bits in Channel Link Control Register DMA4_CLNK_CTRLi
DMA4_CLNK_CTRL_NEXTLCH_ID * (31 << 0)
DMA4_CLNK_CTRLENABLE_LNK * (1 << 15)
; bits in Channel Interrupt Control Register DMA4_CICRi
DMA4_CICR_DROP_IE * (1 << 1)
DMA4_CICR_HALF_IE * (1 << 2)
DMA4_CICR_FRAME_IE * (1 << 3)
DMA4_CICR_LAST_IE * (1 << 4)
DMA4_CICR_BLOCK_IE * (1 << 5)
DMA4_CICR_PKT_IE * (1 << 7)
DMA4_CICR_TRANS_ERR_IE * (1 << 8)
DMA4_CICR_SUPERVISOR_ERR_IE * (1 << 10)
DMA4_CICR_MISALIGNED_ERR_IE * (1 << 11)
DMA4_CICR_DRAIN_IE * (1 << 12)
DMA4_CICR_SUPER_BLOCK_IE * (1 << 14)
; bits in Channel Status Register DMA4_CSRi
DMA4_CSR_DROP * (1 << 1)
DMA4_CSR_HALF * (1 << 2)
DMA4_CSR_FRAME * (1 << 3)
DMA4_CSR_LAST * (1 << 4)
DMA4_CSR_BLOCK * (1 << 5)
DMA4_CSR_SYNC * (1 << 6)
DMA4_CSR_PKT * (1 << 7)
DMA4_CSR_TRANS_ERR * (1 << 8)
DMA4_CSR_SUPERVISOR_ERR * (1 << 10)
DMA4_CSR_MISALIGNED_ADRS_ERR * (1 << 11)
DMA4_CSR_DRAIN_END * (1 << 12)
DMA4_CSR_SUPER_BLOCK * (1 << 14)
; bits in Channel Source Destination Parameters DMA4_CSDPi
DMA4_CSDP_DATA_TYPE * (3 << 0)
DMA4_CSDP_DATA_TYPE_8BIT * (0 << 0)
DMA4_CSDP_DATA_TYPE_16BIT * (1 << 0)
DMA4_CSDP_DATA_TYPE_32BIT * (2 << 0)
DMA4_CSDP_SRC_PACKED * (1 << 6)
DMA4_CSDP_SRC_BURST_EN * (3 << 7)
DMA4_CSDP_SRC_BURST_EN_1B * (0 << 7)
DMA4_CSDP_SRC_BURST_EN_16B * (1 << 7)
DMA4_CSDP_SRC_BURST_EN_32B * (2 << 7)
DMA4_CSDP_SRC_BURST_EN_64B * (3 << 7)
DMA4_CSDP_DST_PACKED * (1 << 13)
DMA4_CSDP_DST_BURST_EN * (3 << 14)
DMA4_CSDP_DST_BURST_EN_1B * (0 << 14)
DMA4_CSDP_DST_BURST_EN_16B * (1 << 14)
DMA4_CSDP_DST_BURST_EN_32B * (2 << 14)
DMA4_CSDP_DST_BURST_EN_64B * (3 << 14)
DMA4_CSDP_WRITE_MODE * (3 << 16)
DMA4_CSDP_WRITE_MODE_WRNP * (0 << 16) ; Write None Posted
DMA4_CSDP_WRITE_MODE_WRP * (1 << 16) ; Write Posted
DMA4_CSDP_WRITE_MODE_LAST_WRNP * (2 << 16) ; Last transfer is Write None Posted
DMA4_CSDP_DST_ENDIAN_LOCK * (1 << 18)
DMA4_CSDP_DST_ENDIAN * (1 << 19)
DMA4_CSDP_SRC_ENDIAN_LOCK * (1 << 20)
DMA4_CSDP_SRC_ENDIAN * (1 << 21)
; bits in Channel Element Number DMA4_CENi
DMA4_CEN_CHANNEL_ELMNT_NBR * &FFFFFF
; bits in Channel Frame Number DMA4_CFNi
DMA4_CFN_CHANNEL_FRAME_NBR * &FFFF
; bits in Channel Source Element Index DMA4_CSEIi
DMA4_CSEI_CHANNEL_SRC_ELMNT_INDEX * &FFFF
; bits in Channel Source Frame Index DMA4_CSFIi
DMA4_CSFI_CH_SRC_FRM_INDEX * &FFFFFFFF
DMA4_CSFI_16BIT_PKT_ELNT_NBR * &FFFF
; bits in Channel Destination Element Index DMA4_CDEIi
DMA4_CDEI_CHANNEL_DST_ELMNT_INDEX * &FFFF
; bits in Channel Destination Frame Index DMA4_CDFIi
DMA4_CDFI_CH_DST_FRM_INDEX * &FFFFFFFF
DMA4_CDFI_16BIT_PKT_ELNT_NBR * &FFFF
; bits in Channel Current Element Number DMA4_CCENi
DMA4_CCEN_CURRENT_ELMNT_NBR * &FFFFFF
; bits in Channel Current Frame Number DMA4_CCFNi
DMA4_CCFN_CURRENT_FRAME_NBR * &FFFF
; IRQ numbers
; Note that various bits of code assume that the IRQs are used for the following purposes:
SDMA_IRQ_0 * OMAP44XX_IRQ_SDMA_0 ; Used for DMA HAL devices/DMAManager
......
......@@ -19,114 +19,151 @@
GET hdr.irqs44xx
UART_THR * &000
UART_RBR * &000
UART_DLL * &000
UART_IER * &004
UART_DLM * &004
UART_IIR * &008
UART_FCR * &008
UART_EFR * &008
UART_LCR * &00C
UART_MCR * &010
UART_THR * &000 ; Transmit Holding Register
UART_RHR * &000 ; Receiver Holding Register
UART_DLL * &000 ; Divisor Latch Low byte
UART_IER * &004 ; Interrupt Enable Register
UART_DLH * &004 ; Divisor Latch High byte
UART_IIR * &008 ; Interrupt Identification Register
UART_FCR * &008 ; FIFO Control Register
UART_EFR * &008 ; Enhanced Feature Register
UART_LCR * &00C ; Line Control Register
UART_MCR * &010 ; Modem Control Register
UART_XON1_ADDR1 * &010
UART_LSR * &014
UART_LSR * &014 ; Line Status Register
UART_XON2_ADDR2 * &014
UART_TCR * &018
UART_TCR * &018 ; Transmission Control Register
UART_XOFF1 * &018
UART_MSR * &018
UART_SPR * &01C
UART_TLR * &01C
UART_MSR * &018 ; Modem Status Register
UART_SPR * &01C ; ScratchPad Register
UART_TLR * &01C ; Trigger Level Register
UART_XOFF2 * &01C
UART_MDR1 * &020
UART_MDR2 * &024
UART_SFLSR * &028
UART_TXFLL * &028
UART_MDR1 * &020 ; Mode Definition Register 1
UART_MDR2 * &024 ; Mode Definition Register 2
UART_SFLSR * &028 ; Status FIFO Line Status Register
UART_TXFLL * &028 ; Transmit Frame Length register Low
UART_RESUME * &02C
UART_TXFLH * &02C
UART_SFREGL * &030
UART_RXFLL * &030
UART_SFREGH * &034
UART_RXFLH * &034
UART_TXFLH * &02C ; Transmit Frame Length register High
UART_SFREGL * &030 ; Status FIFO Register Low
UART_RXFLL * &030 ; Received Frame Length register Low
UART_SFREGH * &034 ; Status FIFO Register High
UART_RXFLH * &034 ; Received Frame Length register High
UART_BLR * &038
UART_UASR * &038
UART_ACREG * &03C
UART_SCR * &040
UART_SSR * &044
UART_UASR * &038 ; UART Autobauding Status Register
UART_ACREG * &03C ; Auxiliary Control Register
UART_SCR * &040 ; Supplementary Control Register
UART_SSR * &044 ; Supplementary Status Register
UART_EBLR * &048
UART_MVR * &050
UART_SYSC * &054
UART_SYSS * &058
UART_WER * &05C
UART_CFPS * &060
UART_MVR * &050 ; Module Version Register
UART_SYSC * &054 ; System Configuration Register
UART_SYSS * &058 ; System Status Register
UART_WER * &05C ; Wake-up Enable Register
UART_CFPS * &060 ; Carrier Frequency Prescaler