Fix HAL_UARTModemControl

Detail:
  s/UART - Fixed HAL_UARTModemControl to pay attention to the 'mask' parameter
Admin:
  Fix was tested on OMAP3 & Iyonix


Version 0.03. Tagged as 'OMAP4-0_03'

VersionNum

-/* (0.02)
+/* (0.03)
  *
  * This file is automatically maintained by srccommit, do not edit manually.
  * Last processed by srccommit version: 1.1.
  *
  */
-#define Module_MajorVersion_CMHG        0.02
+#define Module_MajorVersion_CMHG        0.03
 #define Module_MinorVersion_CMHG        
-#define Module_Date_CMHG                19 Oct 2011
+#define Module_Date_CMHG                04 Dec 2011
 
-#define Module_MajorVersion             "0.02"
-#define Module_Version                  2
+#define Module_MajorVersion             "0.03"
+#define Module_Version                  3
 #define Module_MinorVersion             ""
-#define Module_Date                     "19 Oct 2011"
+#define Module_Date                     "04 Dec 2011"
 
-#define Module_ApplicationDate          "19-Oct-11"
+#define Module_ApplicationDate          "04-Dec-11"
 
 #define Module_ComponentName            "OMAP4"
 #define Module_ComponentPath            "castle/RiscOS/Sources/HAL/OMAP4"
 
-#define Module_FullVersion              "0.02"
-#define Module_HelpVersion              "0.02 (19 Oct 2011)"
-#define Module_LibraryVersionInfo       "0:2"
+#define Module_FullVersion              "0.03"
+#define Module_HelpVersion              "0.03 (04 Dec 2011)"
+#define Module_LibraryVersionInfo       "0:3"

s/UART

@@ -12,7 +12,6 @@
 ; See the License for the specific language governing permissions and
 ; limitations under the License.
 ;
-; This is currently set up to provide only 1 serial port - UART3
 
 	EXPORT	HAL_UARTPorts
 	EXPORT	HAL_UARTStartUp
@@ -389,16 +388,16 @@ HAL_UARTBreak
 
 HAL_UARTModemControl
 	BaseAddr
-	PHPSEI	ip, a3
-	LDRB	a3, [a1, #UART_MCR]
+	PHPSEI	ip, a4
+	LDRB	a4, [a1, #UART_MCR]
 	CMP	a2, #-1
-	AND	a4, a3, #(UART_MCR_DTR + UART_MCR_RTS)	; a4 = relevant bits of current MCR
-	BIC	a3, a3, #(UART_MCR_DTR + UART_MCR_RTS)	; a3 = other bits of current MCR
-	ANDNE	a2, a2, #(UART_MCR_DTR + UART_MCR_RTS)	; a2 = relevant bits on entry
-	ORRNE	a2, a2, a3
-	STRNEB	a2, [a1, #UART_MCR]
+	ORR	a3, a3, #256-(DTR+RTS) ; Only allow DTR+RTS to be modified
+	AND	a2, a2, #DTR+RTS
+	ANDNE	a3, a3, a4
+	EORNE	a3, a3, a2
+	STRNEB	a3, [a1, #UART_MCR]
 	PLP	ip
-	MOV	a1, a4
+	AND	a1, a4, #DTR+RTS
 	MOV	pc, lr