Commit 3ba5ff4b authored by Jeffrey Lee's avatar Jeffrey Lee
Browse files

Implement PL310 device disable & reset entries

Detail:
  s/PL310 - Implemented PL310 disable & reset entries, to allow the L2 cache to be turned off as well as on. Fix potential register corruption from Activate entry (OMAP ROM code may corrupt r0-r12, lr)
Admin:
  Tested on Pandaboard
  Fixes crash on *Cache Off (in conjunction with Kernel-5_35-4_79_2_254)


Version 0.42. Tagged as 'OMAP4-0_42'
parent 797812f8
/* (0.41)
/* (0.42)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.41
#define Module_MajorVersion_CMHG 0.42
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 11 Jan 2015
#define Module_Date_CMHG 17 Jan 2015
#define Module_MajorVersion "0.41"
#define Module_Version 41
#define Module_MajorVersion "0.42"
#define Module_Version 42
#define Module_MinorVersion ""
#define Module_Date "11 Jan 2015"
#define Module_Date "17 Jan 2015"
#define Module_ApplicationDate "11-Jan-15"
#define Module_ApplicationDate "17-Jan-15"
#define Module_ComponentName "OMAP4"
#define Module_ComponentPath "castle/RiscOS/Sources/HAL/OMAP4"
#define Module_FullVersion "0.41"
#define Module_HelpVersion "0.41 (11 Jan 2015)"
#define Module_LibraryVersionInfo "0:41"
#define Module_FullVersion "0.42"
#define Module_HelpVersion "0.42 (17 Jan 2015)"
#define Module_LibraryVersionInfo "0:42"
......@@ -19,6 +19,7 @@
GET Hdr:OSEntries
GET Hdr:HALEntries
GET Hdr:HALDevice
GET Hdr:PL310
GET hdr.omap4430
GET hdr.StaticWS
......@@ -32,6 +33,22 @@
AREA |Asm$$Code|, CODE, READONLY, PIC
MACRO
PL310Sync $regs, $temp
; Errata 753970 requires us to write to a different location when
; performing a sync operation for r3p0
LDR $temp, [$regs, #PL310_REG0_CACHE_ID]
AND $temp, $temp, #&3f
TEQ $temp, #PL310_R3P0
MOV $temp, #0
STREQ $temp, [$regs, #PL310_REG7_CACHE_SYNC_753970]
STRNE $temp, [$regs, #PL310_REG7_CACHE_SYNC]
10
LDR $temp, [$regs, #PL310_REG7_CACHE_SYNC]
TST $temp, #1
BNE %BT10
MEND
PL310_InitDevice ROUT
Push "lr"
......@@ -77,7 +94,7 @@ PL310Desc
ALIGN
PL310Activate
Push "v4-v5, sb, v7-v8, lr"
Push "v1-v5, sb, v7-v8, lr"
; The PL310 L2CC control registers aren't writable from non secure
; modes, so call the OMAP4 HLOS support function (see TRM 27.5.1) to
; get it enabled
......@@ -86,12 +103,29 @@ PL310Activate
DSB SY
SMC #0
MOV a1, #1
Pull "v4-v5, sb, v7-v8, pc"
Pull "v1-v5, sb, v7-v8, pc"
PL310Deactivate
PL310Reset
; Deactivate & reset not implemented
MOV pc, lr
Push "v1-v5, sb, v7-v8, lr"
; Clean cache before disabling it
LDR a2, [a1, #HALDevice_Address]
LDR a1, [a2, #PL310_REG1_AUX_CONTROL]
TST a1, #1<<16
MOV a1, #&FF
ORRNE a1, a1, #&FF00 ; Mask of all ways
STR a1, [a2, #PL310_REG7_CLEAN_WAY]
10
LDR a1, [a2, #PL310_REG7_CLEAN_WAY]
TEQ a1, #0
BNE %BT10
PL310Sync a2, a1
; Now disable the cache
LDR ip, =0x102 ; write control register
MOV a1, #0 ; L2 cache disable
DSB SY
SMC #0
Pull "v1-v5, sb, v7-v8, pc"
PL310Sleep
MOV a1, #0 ; Previously at full power
......
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