Commit 1fa73584 authored by Robert Sprowson's avatar Robert Sprowson
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Enable L2 cache in HAL_Init

On the OMAP4 we're in a privileged but unsecure mode, so to do the initial PL310 enable we call an SMC sunction embedded in the OMAP's onboard mask ROM to do the deed.
Also, correct the range of SDRAM hinted to the kernel - this looks like a copy and paste mistake from the Tungsten HAL.

Version 0.40. Tagged as 'OMAP4-0_40'
parent c19aa5e5
/* (0.39) /* (0.40)
* *
* This file is automatically maintained by srccommit, do not edit manually. * This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1. * Last processed by srccommit version: 1.1.
* *
*/ */
#define Module_MajorVersion_CMHG 0.39 #define Module_MajorVersion_CMHG 0.40
#define Module_MinorVersion_CMHG #define Module_MinorVersion_CMHG
#define Module_Date_CMHG 06 Dec 2014 #define Module_Date_CMHG 21 Dec 2014
#define Module_MajorVersion "0.39" #define Module_MajorVersion "0.40"
#define Module_Version 39 #define Module_Version 40
#define Module_MinorVersion "" #define Module_MinorVersion ""
#define Module_Date "06 Dec 2014" #define Module_Date "21 Dec 2014"
#define Module_ApplicationDate "06-Dec-14" #define Module_ApplicationDate "21-Dec-14"
#define Module_ComponentName "OMAP4" #define Module_ComponentName "OMAP4"
#define Module_ComponentPath "castle/RiscOS/Sources/HAL/OMAP4" #define Module_ComponentPath "castle/RiscOS/Sources/HAL/OMAP4"
#define Module_FullVersion "0.39" #define Module_FullVersion "0.40"
#define Module_HelpVersion "0.39 (06 Dec 2014)" #define Module_HelpVersion "0.40 (21 Dec 2014)"
#define Module_LibraryVersionInfo "0:39" #define Module_LibraryVersionInfo "0:40"
...@@ -406,6 +406,16 @@ HAL_Init ...@@ -406,6 +406,16 @@ HAL_Init
BL SetUpOSEntries BL SetUpOSEntries
; The PL320 L2CC control registers aren't writable from non secure modes on
; this particular Cortex-A9, so call the OMAP4 HLOS support function (see
; TRM 27.5.1) to get it enabled
Push "v4-v5, sb, v7-v8"
LDR ip, =0x102 ; write control register
MOV a1, #1 ; L2 cache enable
DSB SY
SMC #0
Pull "v4-v5, sb, v7-v8"
; Map in the main IO ranges (L3, L4) and then store the offsets to the components ; Map in the main IO ranges (L3, L4) and then store the offsets to the components
; we're interested in ; we're interested in
MOV a1, #0 MOV a1, #0
...@@ -818,8 +828,8 @@ HAL_PhysInfo ...@@ -818,8 +828,8 @@ HAL_PhysInfo
; Do the PhysInfo_WriteTable table output ; Do the PhysInfo_WriteTable table output
Push "v1-v2,lr" Push "v1-v2,lr"
MOV a1, #&80000000 ; Physical RAM from &80000000 and up? MOV a1, #&80000000 ; Up to 2GB physical RAM from &80000000
LDR lr, =&FFFFE000-1 LDR lr, =&FFFFFFFF
STMIA a3, {a1,lr} STMIA a3, {a1,lr}
MOV v1, a2 MOV v1, a2
...@@ -842,7 +852,7 @@ HAL_PhysTable ...@@ -842,7 +852,7 @@ HAL_PhysTable
DCD &00000000, NotPresent :OR: NotAvailable ; GPMC DCD &00000000, NotPresent :OR: NotAvailable ; GPMC
DCD &40000000, IO_Pattern :OR: NotAvailable ; All I/O registers DCD &40000000, IO_Pattern :OR: NotAvailable ; All I/O registers
DCD &80000000, NotPresent :OR: NotAvailable ; SDRC-SMS/SDRAM DCD &80000000, NotPresent :OR: NotAvailable ; SDRC-SMS/SDRAM
DCD &FFFFE000, NotPresent :OR: NotAvailable ; SDRC-SMS/SDRAM DCD &C0000000, NotPresent :OR: NotAvailable ; SDRC-SMS/SDRAM
DCD 0 DCD 0
HAL_Reset HAL_Reset
......
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