Commit 136ab5fd authored by Jeffrey Lee's avatar Jeffrey Lee
Browse files

Disallow EDID writes. Add support for EDID reads which require the segment pointer to be set.

Detail:
  s/I2C - Revise HAL_VideoIICOp implementation to disallow EDID writes (&A0 IIC address). Attempt to write the EDID segment pointer when accessing EDID addresses >= 256.
Admin:
  Builds but untested
  Same code as OMAP3-0_97


Version 0.35. Tagged as 'OMAP4-0_35'
parent dd79dd09
/* (0.34)
/* (0.35)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.34
#define Module_MajorVersion_CMHG 0.35
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 22 Apr 2014
#define Module_Date_CMHG 20 Jul 2014
#define Module_MajorVersion "0.34"
#define Module_Version 34
#define Module_MajorVersion "0.35"
#define Module_Version 35
#define Module_MinorVersion ""
#define Module_Date "22 Apr 2014"
#define Module_Date "20 Jul 2014"
#define Module_ApplicationDate "22-Apr-14"
#define Module_ApplicationDate "20-Jul-14"
#define Module_ComponentName "OMAP4"
#define Module_ComponentPath "castle/RiscOS/Sources/HAL/OMAP4"
#define Module_FullVersion "0.34"
#define Module_HelpVersion "0.34 (22 Apr 2014)"
#define Module_LibraryVersionInfo "0:34"
#define Module_FullVersion "0.35"
#define Module_HelpVersion "0.35 (20 Jul 2014)"
#define Module_LibraryVersionInfo "0:35"
......@@ -732,7 +732,7 @@ read_bytes
; int HAL_VideoIICOp(uint32_t op, uint8_t *buffer, uint32_t *size)
; in:
; r0 = b0-15 offset within IIC device to start at (currently assumed 8 bit)
; r0 = b0-15 offset within IIC device to start at
; b16-23 base IICAddress
; b24-31 zero
; r1 = buffer to read from/write to
......@@ -749,37 +749,51 @@ HAL_VideoIICOp
STREQ ip, [a3]
MOVEQ a1, #IICStatus_Error
MOVEQ pc, lr
; Check for input passed end
UBFX a4, a1, #0, #16
CMP a4, #256
STRCS ip, [a3]
MOVCS a1, #IICStatus_Completed
MOVCS pc, lr
; Clip request at end
; Check if this is an EDID read or write
UBFX a4, a1, #16, #8
TEQ a4, #&a0 ; Don't allow writing to EDID for safety reasons
STREQ ip, [a3]
MOVEQ a1, #IICStatus_Error
MOVEQ pc, lr
TEQ a4, #&a1
TSTNE a1, #&ff00 ; If not EDID read, limit to 0-255 offset in device
STRNE ip, [a3]
MOVNE a1, #IICStatus_Completed
MOVNE pc, lr
Push "a1-a3,lr"
LDR a3, [a3]
ADD ip, a4, a3
CMP ip, #256
RSBHI a3, a4, #256
; Build a set of iic_transfer blocks and call RISCOS_IICOpV
; We construct two iic_transfer blocks
; - First block is a single byte write containing the start address (lower 8 bits of r0)
; - Second block is a read. r2 bytes written to r1.
; Block 2:
; We construct (up to) three iic_transfer blocks
; - First block is an (optional) single byte write to the EDID segment pointer
; - Second block is a single byte write containing the start address (lower 8 bits of r0)
; - Third block is a read. r2 bytes written to r1.
; The E-EDID EEPROM spec says that the segment pointer should auto-increment when a sequential (i.e. block) read occurs, so we shouldn't have to worry about splitting requests into 256 byte blocks and manually writing the pointer each time.
; Block 3:
UBFX a1, a1, #16, #8 ; Extract base IICAddress
Push "a1-a3" ; Push the block on the stack (a2 & a3 are already correct)
; Block 1:
; Block 2:
BIC a1, a1, #1 ; Clear RnW of base address
ADD a2, sp, #12 ; sp+12 should point to the 8 bit offset
MOV a3, #1
Push "a1-a3"
; Block 1:
MOV a1, #&60 ; Write to segment pointer
ADD a2, a2, #1 ; With bits 8-15 of the offset
Push "a1-a3"
; Work out if block 1 is needed or not
LDR a2, [sp, #36] ; Get r0
TST a2, #&ff00 ; If segment == 0
MOVEQ a2, #0 ; ... then avoid matching address &A0/&A1
AND a2, a2, #&fe0000
TEQ a2, #&a00000
; Now attempt to start the transfer
LDRB a2, [sb, #BoardConfig_VideoI2C]
MOV a2, a2, LSL #24
ADD a2, a2, #2
ADD a2, a2, #3
MOV a1, sp
SUBNE a2, a2, #1 ; Skip block 1 if segment == 0 or not EDID addr
ADDNE a1, a1, #12
; If HAL_Init isn't done yet, we can't use RISCOS_IICOpV
LDR a3, HALInitialised
CMP a3, #0
......@@ -792,9 +806,9 @@ HAL_VideoIICOp
20
; In case of error, assume nothing got transferred at all
CMP a1, #IICStatus_Completed
LDREQ a4, [sp, #(3*4)+(2*4)] ; Clipped block 2 request size
LDREQ a4, [sp, #(12*2)+(2*4)] ; Block 3 request size
MOVNE a4, #0
ADD sp, sp, #24 ; Junk the iic_transfer blocks
ADD sp, sp, #12*3 ; Junk the iic_transfer blocks
STR a1, [sp, #0] ; Propagate return code
LDR a3, [sp, #8]
STR a4, [a3] ; Actual transfer size
......
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