GPIO corrections

Detail:
  Correct group number for pin 58.
  Use OMAP44x0 register names for interrupt handling, the status registers are split into set/clear pairs.
Admin:
  Submission from Willi Theiss.

Version 0.59. Tagged as 'OMAP4-0_59'

VersionNum

-/* (0.58)
+/* (0.59)
  *
  * This file is automatically maintained by srccommit, do not edit manually.
  * Last processed by srccommit version: 1.1.
  *
  */
-#define Module_MajorVersion_CMHG        0.58
+#define Module_MajorVersion_CMHG        0.59
 #define Module_MinorVersion_CMHG        
-#define Module_Date_CMHG                01 Apr 2018
+#define Module_Date_CMHG                08 Apr 2018
 
-#define Module_MajorVersion             "0.58"
-#define Module_Version                  58
+#define Module_MajorVersion             "0.59"
+#define Module_Version                  59
 #define Module_MinorVersion             ""
-#define Module_Date                     "01 Apr 2018"
+#define Module_Date                     "08 Apr 2018"
 
-#define Module_ApplicationDate          "01-Apr-18"
+#define Module_ApplicationDate          "08-Apr-18"
 
 #define Module_ComponentName            "OMAP4"
 #define Module_ComponentPath            "castle/RiscOS/Sources/HAL/OMAP4"
 
-#define Module_FullVersion              "0.58"
-#define Module_HelpVersion              "0.58 (01 Apr 2018)"
-#define Module_LibraryVersionInfo       "0:58"
+#define Module_FullVersion              "0.59"
+#define Module_HelpVersion              "0.59 (08 Apr 2018)"
+#define Module_LibraryVersionInfo       "0:59"

hdr/GPIOPadConf

@@ -282,7 +282,7 @@ GPIOAlts1
         PinBelongsTo GPIOType_GPIO, 57, AltGPIO    ; GPIO (TVDETECT)
         PinEnd
         PinStart     58, I
-        PinBelongsTo GPIOType_GPIO, 57, AltGPIO    ; GPIO (TV_SHORT)
+        PinBelongsTo GPIOType_GPIO, 58, AltGPIO    ; GPIO (TV_SHORT)
         PinEnd
         PinStart     59, IO
         PinBelongsTo GPIOType_GPIO, 59, AltGPIO    ; GPIO

s/GPIO

@@ -40,12 +40,12 @@
 GPIO_Init
         ; Don't bother resetting the controllers for now, just make sure no IRQs are enabled
         ADR     a1, L4_GPIO_Table
-        MOV     a2, #6
-        MOV     a3, #0
+        MOV     a2, #GPIO_PORT_MAX
+        MVN     a3, #0
 10
         LDR     a4, [a1], #4
         SUBS    a2, a2, #1
-        STR     a3, [a4, #GPIO_IRQENABLE1]
+        STR     a3, [a4, #GPIO_IRQSTATUS_CLR_0]
         BNE     %BT10
         MOV     pc, lr
 
@@ -102,7 +102,7 @@ GPIOx_SetAndEnableIRQ
         ORR     a1, a1, a4 ; set pin as input
         STR     a2, [a3, #GPIO_LEVELDETECT0]
         STR     a1, [a3, #GPIO_OE]
-        STR     a4, [a3, #GPIO_SETIRQENABLE1]
+        STR     a4, [a3, #GPIO_IRQSTATUS_SET_0]
         MSR     CPSR_c, ip ; interrupts restored
         MOV     pc, lr
 
@@ -255,7 +255,7 @@ GPIOFreeToUse
         DCD     2_00001000001000000000000000000000
         ASSERT  (. - GPIOFreeToUse):SHR:2 = (GPIOType_Max * GPIO_PORT_MAX)
 
-        ; Init the GPIO HAL device
+        ; Init our GPIO HAL devices
         ; a1 = BoardType value
         ; a2 = BoardRevision value
 GPIO_InitDevices ROUT
@@ -516,8 +516,8 @@ GPIOEdgePollStatus ROUT
         LDR     a3, [a1, #HALDevice_Address]
         LDR     a4, [a1, #WkspValidMask]
         ANDS    a2, a4, a2              ; Ensure bits being cleared are valid
-        LDR     a1, [a3, #GPIO_IRQSTATUS1]
-        STRNE   a2, [a3, #GPIO_IRQSTATUS1]
+        LDR     a1, [a3, #GPIO_IRQSTATUS_0]
+        STRNE   a2, [a3, #GPIO_IRQSTATUS_0]
         MOV     pc, lr
 
 ; enum HAL_GPIOReadMode(struct gpiodevice *, int pin)