Commits (1)
  • Robert Sprowson's avatar
    Add support for POR detection. · ffb0062a
    Robert Sprowson authored
    Harder than it should have been because someone wired the reset button up to the cold reset pin.
    Now gets the OSStartFlags right so that delete-power-on et al are respected by the kernel.
    
    Version 0.57. Tagged as 'OMAP3-0_57'
    ffb0062a
......@@ -11,13 +11,13 @@
GBLS Module_HelpVersion
GBLS Module_ComponentName
GBLS Module_ComponentPath
Module_MajorVersion SETS "0.56"
Module_Version SETA 56
Module_MajorVersion SETS "0.57"
Module_Version SETA 57
Module_MinorVersion SETS ""
Module_Date SETS "07 Jan 2012"
Module_ApplicationDate SETS "07-Jan-12"
Module_Date SETS "15 Jan 2012"
Module_ApplicationDate SETS "15-Jan-12"
Module_ComponentName SETS "OMAP3"
Module_ComponentPath SETS "castle/RiscOS/Sources/HAL/OMAP3"
Module_FullVersion SETS "0.56"
Module_HelpVersion SETS "0.56 (07 Jan 2012)"
Module_FullVersion SETS "0.57"
Module_HelpVersion SETS "0.57 (15 Jan 2012)"
END
/* (0.56)
/* (0.57)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.56
#define Module_MajorVersion_CMHG 0.57
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 07 Jan 2012
#define Module_Date_CMHG 15 Jan 2012
#define Module_MajorVersion "0.56"
#define Module_Version 56
#define Module_MajorVersion "0.57"
#define Module_Version 57
#define Module_MinorVersion ""
#define Module_Date "07 Jan 2012"
#define Module_Date "15 Jan 2012"
#define Module_ApplicationDate "07-Jan-12"
#define Module_ApplicationDate "15-Jan-12"
#define Module_ComponentName "OMAP3"
#define Module_ComponentPath "castle/RiscOS/Sources/HAL/OMAP3"
#define Module_FullVersion "0.56"
#define Module_HelpVersion "0.56 (07 Jan 2012)"
#define Module_LibraryVersionInfo "0:56"
#define Module_FullVersion "0.57"
#define Module_HelpVersion "0.57 (15 Jan 2012)"
#define Module_LibraryVersionInfo "0:57"
......@@ -53,7 +53,7 @@ MoreDebug SETL Debug :LAND: {FALSE}
IMPORT DebugHALPrint
IMPORT DebugHALPrintReg
IMPORT DebugHALPrintByte
; IMPORT generate_POR_flags
IMPORT SDMA_Had_POR
IMPORT RTC_Init
IMPORT DebugCallstack
IMPORT TPSRead
......@@ -121,10 +121,14 @@ no_cs0
CallOSM OS_AddRAM
no_cs1
DebugChar v1,v2,71
MOV a4, a1
MOV a1, #OSStartFlag_RAMCleared
MOV v1, a1
BL SDMA_Had_POR
CMP a1, #0
MOVNE a1, #OSStartFlag_RAMCleared :OR: OSStartFlag_POR
MOVEQ a1, #OSStartFlag_RAMCleared
ADRL a2, HAL_Base + OSROM_HALSize ; a2 -> RISC OS image
ADR a3, HALdescriptor
MOV a4, v1
CallOSM OS_Start
......
......@@ -232,8 +232,10 @@ clear_ram
ADD v5, v5, #DMA4_i
LDR v1, =&1014000 ; Constant fill, post-increment destination, source synchronised
STR v1, [v5, #DMA4_CCRi]
LDR v1, [v5, #DMA4_CLNK_CTRLi]
BIC v1, v1, #&8000 ; Disable channel linking
STR v1, [v5, #DMA4_CLNK_CTRLi]
MOV v1, #0
STR v1, [v5, #DMA4_CLNK_CTRLi] ; Disable channel linking
STR v1, [v5, #DMA4_COLORi] ; Clear colour of 0. Although the clear colour register only holds a 24 bit value, the MSB (for 4-byte DMA) is always written as 0.
MOV v1, #1<<4
STR v1, [v5, #DMA4_CICRi] ; frame end interrupt enabled
......
......@@ -32,6 +32,7 @@
AREA |Asm$$Code|, CODE, READONLY, PIC
EXPORT SDMA_Init
EXPORT SDMA_Had_POR
IMPORT memcpy
IMPORT DebugHALPrint
......@@ -63,6 +64,41 @@ string SETS "::" :CC: "$r" :CC: ": "
DebugReg $temp, $string
MEND
SDMA_Had_POR
; Called pre MMU enable and pre SDMA_Init!
;
; In an ideal world we'd just read the PRM_RSTST.GLOBALCOLD_RST to
; figure out what the last reset reason was, but the BeagleBoard has
; erroneously wired the reset button to the SYS_nRESPWRON instead of
; the SYS_nRESWARM pin. This means both power on resets and pressing
; the reset button set the GLOBALCOLD_RST bit.
; So we need to find some bits that aren't cleared to known values on
; a cold reset - and there aren't many - the internal SRAM is all
; reused by the ROM bootloader.
;
; However, the SDMA does have some control bits that are implemented
; as SRAM (and hence not defined on power up), so we seed them with a
; statistically unlikely number and compare this key on startup to
; decide which reset type it is.
;
; Register DMA4_CLNK_CTRLi isn't being used and it has up to 5 bits
; per channel to play with. Use a 32 bit key spread 4 bits a piece.
MOV a1, #0
LDR a2, =L4_sDMA + DMA4_i + DMA4_CLNK_CTRLi
LDR a4, =&ABCD1234
10
; Compare 4 bits read with the key, and accumulate the result
LDR ip, [a2]
EOR a3, ip, a4
ORR a1, a1, a3, LSL #32-4
; Write 4 bits from the key while we're passing
BFI ip, a4, #0, #4
STR ip, [a2], #DMA4_CHANNEL_SIZE
MOVS a4, a4, LSR #4
BNE %BT10
MOV pc, lr
SDMA_Init
Push "v1-v4,lr"
; Do basic reset of SDMA controller, then register the HAL devices
......@@ -492,8 +528,10 @@ SDMAReset
LDR a3, [a2, #DMA4_CCRi]
TST a3, #(1<<9) :OR: (1<<10) ; Check RD_ACTIVE & WR_ACTIVE
BNE %BT10
LDR a4, [a2, #DMA4_CLNK_CTRLi]
BIC a4, a4, #&8000 ; Disable channel linking
STR a4, [a2, #DMA4_CLNK_CTRLi]
MVN a4, #0
STR a1, [a2, #DMA4_CLNK_CTRLi] ; Disable channel linking
STR a1, [a2, #DMA4_CICRi] ; Disable all interrupts
STR a4, [a2, #DMA4_CSRi] ; Reset interrupt status bits
; These registers don't really need to be reset, because we'll reprogram them as and when needed.
......