Commit f84ef1c2 authored by Robert Sprowson's avatar Robert Sprowson Committed by ROOL

On Pi 4's with no VL805 firmware EEPROM, softload it

Some Pi 4's - for example, the recently released 8GB variant - don't have the firmware EEPROM on the VL805 fitted. The VideoCore loads default firmware on power on in order to do USB booting, but when RISC OS takes over and does a PCI fundamental reset the VL805 ends up with no firmware running.
Detect this (by peeking the firmware version) and use the NotifyXHCIReset mailbox message to cause the VideoCore to softload the firmware again. Earlier built PCBs *do* contain a firmware EEPROM and skip the mailbox message.

By inspection with a prototype version in BASIC it appears the SCB access needs to be enabled for this to work, it previously wasn't, hence the extra PCI setup step.

Also, reduce the PCI reset delay and rename PCIe_RGR1_SW_INIT1_POWERDOWN to more accurately reflect what it does.

Version 0.89. Tagged as 'HAL_BCM2835-0_89'
parent 227406f6
/* (0.88)
/* (0.89)
*
* This file is automatically maintained by srccommit, do not edit manually.
*
*/
#define Module_MajorVersion_CMHG 0.88
#define Module_MajorVersion_CMHG 0.89
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 01 Jul 2020
#define Module_Date_CMHG 01 Aug 2020
#define Module_MajorVersion "0.88"
#define Module_Version 88
#define Module_MajorVersion "0.89"
#define Module_Version 89
#define Module_MinorVersion ""
#define Module_Date "01 Jul 2020"
#define Module_Date "01 Aug 2020"
#define Module_ApplicationDate "01-Jul-20"
#define Module_ApplicationDate "01-Aug-20"
#define Module_ComponentName "HAL_BCM2835"
#define Module_FullVersion "0.88"
#define Module_HelpVersion "0.88 (01 Jul 2020)"
#define Module_LibraryVersionInfo "0:88"
#define Module_FullVersion "0.89"
#define Module_HelpVersion "0.89 (01 Aug 2020)"
#define Module_LibraryVersionInfo "0:89"
......@@ -933,11 +933,14 @@ V3D_Base * &00500000
; PCIe
PCIe_Base * &01500000
PCIe_BRIDGE_CFG * 0
PCIe_BRIDGE_CFG * 0 ; Standard config space for the built-in bridge
PCIe_MISC_CTRL * &4008
PCIe_MISC_CTRL_SCV_ACCESS_EN * 1:SHL:12
PCIe_MISC_CTRL_SCB_ACCESS_EN * 1:SHL:12
PCIe_MISC_CTRL_CFG_READ_SAFE * 1:SHL:13
PCIe_MISC_CTRL_MAX_BURST_SHIFT * 20
PCIe_MISC_CTRL_SCB0_SIZE_SHIFT * 27 ; 5b values
PCIe_MISC_CTRL_SCB1_SIZE_SHIFT * 22
PCIe_MISC_CTRL_SCB2_SIZE_SHIFT * 0
PCIe_PCI_MEM_LO_WIN0 * &400C
PCIe_PCI_MEM_HI_WIN0 * &4010
PCIe_PCI_MEM_LO_WIN1 * &4014
......@@ -946,12 +949,12 @@ PCIe_PCI_MEM_LO_WIN2 * &401C
PCIe_PCI_MEM_HI_WIN2 * &4020
PCIe_PCI_MEM_LO_WIN3 * &4024
PCIe_PCI_MEM_HI_WIN3 * &4028
PCIe_RC_CONFIG_LO_BAR1 * &402C
PCIe_RC_CONFIG_HI_BAR1 * &4030
PCIe_RC_CONFIG_LO_BAR1 * &402C ; For inbound memory
PCIe_RC_CONFIG_HI_BAR1 * &4030 ; transfers PCI->GISB
PCIe_RC_CONFIG_LO_BAR2 * &4034 ; For inbound memory
PCIe_RC_CONFIG_HI_BAR2 * &4038 ; transfers PCI->CPU
PCIe_RC_CONFIG_LO_BAR3 * &403C
PCIe_RC_CONFIG_HI_BAR3 * &4040
PCIe_RC_CONFIG_LO_BAR3 * &403C ; For inbound memory
PCIe_RC_CONFIG_HI_BAR3 * &4040 ; transfers PCI->SCB
PCIe_LINK_STATUS * &4068
PCIe_LINK_STATUS_PORT * 1:SHL:7
PCIe_LINK_STATUS_IN_L23 * 1:SHL:6
......@@ -985,7 +988,7 @@ PCIe_EXT_CFG_INDEX_BUS_SHIFT * 20
PCIe_EXT_CFG_INDEX_DEV_SHIFT * 15
PCIe_EXT_CFG_INDEX_FN_SHIFT * 12
PCIe_RGR1_SW_INIT1 * &9210
PCIe_RGR1_SW_INIT1_POWERDOWN * 1:SHL:1
PCIe_RGR1_SW_INIT1_INIT * 1:SHL:1
PCIe_RGR1_SW_INIT1_RESET * 1:SHL:0
; Gigabit Ethernet
......
......@@ -27,15 +27,19 @@
;
GET Hdr:ListOpts
GET Hdr:CPU.Arch
GET Hdr:Macros
GET Hdr:Proc
GET Hdr:System
GET Hdr:FSNumbers
GET Hdr:NewErrors
GET Hdr:PCI
GET Hdr:BCMSupport
GET hdr.CastleMacros
GET hdr.BCM2835
GET hdr.StaticWS
IMPORT HAL_CounterDelay
IMPORT HAL_SendHostMessage
IMPORT memcpy
EXPORT PCI_Init
EXPORT HAL_PCIReadConfigByte
......@@ -52,7 +56,7 @@
; Timeouts
PCILinkUpTries * 1000
PCILinkUpDelay * 1000 ; Microseconds
PCIResetDelay * 1000 ; Microseconds
PCIResetDelay * 250 ; Microseconds
; Config layout
PCIViaMemBase * &00100000 ; Non-zero, just so nobody thinks it's disabled
......@@ -61,6 +65,9 @@ PCIWinMemBaseLo * &00000000 ; PCI view offset
CPUWinMemBaseHi * 6
CPUWinMemBaseLo * &00000000 ; CPU view offset
CPUWinMemSize * &08000000 ; Arbitrary, but at least big enough to encompass &00000000...PCIViaMemBase
PCIIBOffsetHi * 0
PCIIBOffsetLo * &00000000 ; PCI inbound offset to CPU physical address
PCIIBSizeLog2 * 32
PCI_Init ROUT
CPUDetect a1
......@@ -75,16 +82,37 @@ PCI_Init ROUT
; First get into a known state in case of a soft reset
LDR v2, =PCIe_RGR1_SW_INIT1
LDR a1, [v1, v2]
ORR a1, a1, #PCIe_RGR1_SW_INIT1_POWERDOWN :OR: PCIe_RGR1_SW_INIT1_RESET
ORR a1, a1, #PCIe_RGR1_SW_INIT1_INIT :OR: PCIe_RGR1_SW_INIT1_RESET
STR a1, [v1, v2]
MOV a1, #PCIResetDelay
BL HAL_CounterDelay
; Power up the controller
; Take the bridge out of reset
LDR a4, [v1, v2]
BIC a4, a4, #PCIe_RGR1_SW_INIT1_POWERDOWN
BIC a4, a4, #PCIe_RGR1_SW_INIT1_INIT
STR a4, [v1, v2]
; Set up RC BARs
; BAR1 = unused
; BAR2 = inbound (limited to bottom 3GB per https://www.spinics.net/lists/arm-kernel/msg740693.html)
; BAR3 = unused
LDR a3, =PCIe_RC_CONFIG_LO_BAR1
MOV a1, #0 ; Size
STR a1, [a3, v1]!
MOV a2, #PCIIBOffsetHi
STR a2, [a3, #PCIe_RC_CONFIG_HI_BAR2 - PCIe_RC_CONFIG_LO_BAR1]
ASSERT PCIIBSizeLog2 > 15
LDR a2, =PCIIBOffsetLo :OR: (PCIIBSizeLog2 - 15) ; Size
STR a2, [a3, #PCIe_RC_CONFIG_LO_BAR2 - PCIe_RC_CONFIG_LO_BAR1]
STR a1, [a3, #PCIe_RC_CONFIG_LO_BAR3 - PCIe_RC_CONFIG_LO_BAR1]
; Set SCB0 size and access
LDR a1, =((PCIIBSizeLog2 - 15):SHL:PCIe_MISC_CTRL_SCB0_SIZE_SHIFT) :OR: PCIe_MISC_CTRL_SCB_ACCESS_EN
LDR a3, =PCIe_MISC_CTRL
STR a1, [v1, a3]
; Knock out the unused controller interrupts
MVN a1, #0
LDR a3, =PCIe_INTR2_CLEAR
......@@ -123,7 +151,7 @@ PCI_Init ROUT
LDREQH a1, [v1, #PCIe_BRIDGE_CFG + PCIConf_VendorID]
MOVWEQ a2, #&14E4 ; Broadcom
TEQEQ a1, a2
LDREQB a1, [v1, #PCIConf_HeaderType]
LDREQB a1, [v1, #PCIe_BRIDGE_CFG + PCIConf_HeaderType]
TEQEQ a1, #1 ; Bridge
Pull "v1-v3, pc",NE
......@@ -173,6 +201,12 @@ PCI_Init ROUT
MOV a1, #0 ; VL805 is dev/bus/fn 0
BL HAL_PCIWriteConfigByte
MOV a3, #&50 ; Non-standard offset to FW version number
MOV a2, #0
MOV a1, #0 ; VL805 is dev/bus/fn 0
BL HAL_PCIReadConfigWord
MOV v2, a1
; PCI side of outbound window
MOV a1, #PCIWinMemBaseLo
LDR a3, =PCIe_PCI_MEM_LO_WIN0
......@@ -194,7 +228,38 @@ PCI_Init ROUT
ORR a1, a1, a4, LSL #PCIe_CPU_MEM_BASE_SHIFT
STR a1, [a3, #PCIe_CPU_MEM_BASE_LIMIT_WIN0 - PCIe_PCI_MEM_LO_WIN0]
; If the firmware version was unset assume our PCI fundamental reset wiped
; what was loaded and this Pi has no EEPROM for the VL805 to reload from.
; Notify the VideoCore to softload the firmware baked into 'start4.elf'.
TEQ v2, #0
Pull "v1-v3, pc", NE
ADR a1, tagbuffer + 12
BIC a1, a1, #15 ; Mailbox alignment
ADR a2, %FT30
MOV a3, #NotifyMsgLen
BL memcpy
CallOS OS_LogToPhys
MOV a2, a1
MOV a1, #MB_Chan_ARM2VC
BL HAL_SendHostMessage
MOV a1, #1000 ; Wait for VL805 to boot
BL HAL_CounterDelay
Pull "v1-v3, pc"
30
DCD NotifyMsgLen
DCD 0 ; Process request
DCD ARM2VC_Tag_NotifyXHCIReset
DCD 4 ; Tag buffer size
DCD 4 ; Request
DCD (1:SHL:20) :OR: (0:SHL:15) :OR: (0:SHL:12) ; On bus 1/devfn 0
DCD ARM2VC_Tag_End
40
NotifyMsgLen * %BT40 - %BT30
HAL_PCIWriteConfigByte ROUT
MOV ip, #-1
......
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