Commit bd94ab11 authored by Ben Avison's avatar Ben Avison

Address of mailbox given to GPU should have cacheability bits set correctly

On entry to HAL_SendHostMessage, we ensure the contents of the mailbox buffer
are flushed out to the ARM L2 cache (if applicable) and main memory. There
were a couple of instructions to fill in the top two bits of the address
before passing it to the VC, but they were commented out for reasons that are
not clear.

The effect of this is that the VC will look in its L1 and L2 caches for the
data in the buffer. On Pi 1 and 0, this wouldn't be too bad, since ARM11
didn't have its own L2 cache and would have written the data into the VC L2
cache instead, meaning that there would only be coherencency problems if the
VC L1 cache still contained the old contents of the address. On Pi 2-4, it's
more risky, because the VC L2 cache could also be inconsistent with main
memory at this point.

Reinstating the top two bits doesn't appear to cause any ill effects I can
see (tested on Pi 1 and 4), so put these instructions back in.
parent 12a389b2
......@@ -4,18 +4,18 @@
*
*/
#define Module_MajorVersion_CMHG 0.79
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 18 Jun 2019
#define Module_MinorVersion_CMHG MailboxCacheCoherence.1
#define Module_Date_CMHG 02 Aug 2019
#define Module_MajorVersion "0.79"
#define Module_Version 79
#define Module_MinorVersion ""
#define Module_Date "18 Jun 2019"
#define Module_MinorVersion "MailboxCacheCoherence.1"
#define Module_Date "02 Aug 2019"
#define Module_ApplicationDate "18-Jun-19"
#define Module_ApplicationDate "02-Aug-19"
#define Module_ComponentName "HAL_BCM2835"
#define Module_FullVersion "0.79"
#define Module_HelpVersion "0.79 (18 Jun 2019)"
#define Module_FullVersion "0.79 (MailboxCacheCoherence.1)"
#define Module_HelpVersion "0.79 (02 Aug 2019) MailboxCacheCoherence.1"
#define Module_LibraryVersionInfo "0:79"
......@@ -92,8 +92,8 @@ RAM_Base * &00000000 ; try off bottom
Boot_RAM_Base * &00000000
DMA_RAM_Base * &C0000000 ; base physical address of ram for DMA purposes
GPU_UnCached * &c0000000 ; GPU mempry mapping uncached
GPU_L2Conly * &80000000 ; GPU L2 Cached (only)
GPU_L2CnonAl * &40000000 ; GPU L2 cached non allocating coherent
GPU_L2Conly * &80000000 ; GPU L2 Cached (only; non-allocating on Pi 4)
GPU_L2CnonAl * &40000000 ; GPU L2 cached non allocating coherent (undefined on Pi 4)
GPU_L1L2Cac * &00000000 ; both L1 and L2 cached GPU side
GPU_CacheMask * &c0000000
......
......@@ -74,8 +74,8 @@ HAL_SendHostMessage ROUT
; send message
TEQ r1, #0
BICNE r1, r1, #&c0000000
; LDRNE r2, FB_CacheMode
; ORRNE r1, r1, r2
LDRNE r2, FB_CacheMode
ORRNE r1, r1, r2
ORR r2, r0, r1
AND r1, r0, #&f ; isolate channel number
STR r2,[r3, #MB_ChWr]
......
......@@ -40,7 +40,6 @@
EXPORT VCHIQ_InitDevices
IMPORT HAL_SendHostMessage
IMPORT memcpy
MACRO
......
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