; ; Copyright (c) 2012, RISC OS Open Ltd ; Copyright (c) 2012, Adrian Lees ; All rights reserved. ; ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions are met: ; * Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; * Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; * Neither the name of RISC OS Open Ltd nor the names of its contributors ; may be used to endorse or promote products derived from this software ; without specific prior written permission. ; ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ; With many thanks to Broadcom Europe Ltd for releasing the source code to ; its Linux drivers, thus making this port possible. ; [ :LNOT: :DEF: BCM2835_Hdr GBLL BCM2835_Hdr ; Debugging in the serial port (HAL_DebugTX, HAL_DebugRX) GBLL Debug Debug SETL {FALSE} ; Debug messages from the HAL itself GBLL HALDebug HALDebug SETL {FALSE} :LAND: Debug ; Drive the GPIO serial pins using 16550-like mini-UART, rather than ; the PL011-line UART0. The mini-uart is less capable in many ways ; (less configurable, smaller FIFOs, can't cope with VPU clock varying) ; so we may eventaully want to follow the default Raspbian behaviour of ; only using it for boards where UART0 is better used to drive the ; Bluetooth chip. This would invole changing this to a run-time switch. GBLL MiniUART MiniUART SETL {FALSE} ; Enable JTAG support ; ; This reconfigures GPIO22-27 into alt4 mode, which maps the ARM JTAG ; signals to the following pins on the 40-pin GPIO header that's ; found on the B+ and later models: ; ; GPIO22 ARM_TRST pin 15 ; GPIO23 ARM_RTCK pin 16 ; GPIO24 ARM_TDO pin 18 ; GPIO25 ARM_TCK pin 22 ; GPIO26 ARM_TDI pin 37 ; GPIO27 ARM_TMS pin 13 ; ; If you want to debug an older board then you'll have to adjust the ; code accordingly (n.b. revision 1 boards for Pi 1B only have ARM_TDI ; available via the camera header, which will be awkward to get ; access to) ; ; As a precaution, this setting will also disable registration of the ; GPIO HAL device GBLL JTAG JTAG SETL {FALSE} ; RPi ARM11 registers ; 4Gbytes of address space. ; 00000000-0000001F reserved for exception vectors ; FFFFE000-FFFFFFFF allocated to control registers ; Bus memory map, for direct DMA access to devices ; 7e000000-7effffff I/O peripherals for DMA access ; c0000000-???????? SDRAM physical for DMA ; Our physical memory map: ; 00000000-???????? SDRAM upper bound set at boot ; 20000000-20ffffff IO_Base for peripherals ; 3fffffff top of physical memory space ; Address window 0 is set to 4K and points to a single page of HAL workspace for the messaging ; unit. ;ROM_Base * &00000000 IO_Base_BCM2835 * &20000000 IO_Base_BCM2836 * &3F000000 ; it moves in Pi 2 IO_Base_BCM2838 * &FE000000 ; and again in Pi 4 IO_Base2_BCM2838 * &FC000000 ; Pi 4 adds a second range of peripherals IO_Size_BCM2835 * &01000000 IO_Size_BCM2838 * &01800000 IO_Size2_BCM2838 * &02000000 PCIe_Base_Hi * &06 PCIe_Base_Lo * &00000000 PCIe_Size_Hi * &02 PCIe_Size_Lo * &00000000 RAM_Base * &00000000 ; try off bottom Boot_RAM_Base * &00000000 DMA_RAM_Base * &C0000000 ; base physical address of ram for DMA purposes GPU_UnCached * &c0000000 ; GPU mempry mapping uncached GPU_L2Conly * &80000000 ; GPU L2 Cached (only; non-allocating on Pi 4) GPU_L2CnonAl * &40000000 ; GPU L2 cached non allocating coherent (undefined on Pi 4) GPU_L1L2Cac * &00000000 ; both L1 and L2 cached GPU side GPU_CacheMask * &c0000000 ; Exit CC if ARM11, EQ if A7/A53, HI if A72, CS if A7/A53/A72 MACRO $label CPUDetect $reg $label MRC p15, 0, $reg, c0, c0, 0 ; read Main ID Register ; xxxxB76x for ARM1176, xxxxC07x for Cortex-A7, xxxxD03x for Cortex-A53, xxxxD08x for Cortex-A72 UXTH $reg, $reg MOV $reg, $reg, LSR #4 SUB $reg, $reg, #&C07 :AND: &F SUBS $reg, $reg, #&C07 :AND: &FF0 TEQNE $reg, #&D03 - &C07 MEND ; Acquire/release the HAL spinlock ; This is mainly for quad-core devices, but will work with ARMv6 too MACRO AcquireSpinlock ; Corrupts ip, NZ, stashes old PSR on stack MRS ip, CPSR Push "ip" ADD sb, sb, #:INDEX:Spinlock CPSID if 10 LDREX ip, [sb] TEQ ip, #0 WFENE STREXEQ ip, sb, [sb] TEQEQ ip, #0 BNE %BT10 MCR p15, 0, ip, c7, c10, 5 ; a.k.a DoMemBarrier, but ip already 0 SUB sb, sb, #:INDEX:Spinlock MEND MACRO ReleaseSpinlock ; Corrupts ip MOV ip, #0 MCR p15, 0, ip, c7, c10, 5 ; a.k.a DoMemBarrier, but ip already 0 STR ip, Spinlock ; Clear spinlock before barrier MCR p15, 0, ip, c7, c10, 4 ; a.k.a DataSyncBarrier, but ip already 0 SEV Pull "ip" MSR CPSR_c, ip MEND ; ; Timer details ; TIMER_RATE * 1000000 ; 1MHz GBLA NumTimers NumTimers SETA 0 MACRO DeclareTimer $phys TimerPhysFromLog$NumTimers * $phys NumTimers SETA NumTimers + 1 MEND ; List of physical timers (excluding those already used by VideoCore) ; in the order we use them for logical timers DeclareTimer 1 DeclareTimer 3 ; An assembly-time variable for looping over all logical timers, since ; the available timers might vary with version of start.elf GBLA Timer ; ; Mailbox ; ; There are two mailboxes; we write to mailbox 1 and read from mailbox 0 ; MB_Base * &0000b800 ; offset from IO space start MB_DBell0 * &40 ; doorbell 0 (VCHIQ VC -> ARM) MB_DBell1 * &44 ; doorbell 1 MB_DBell2 * &48 ; doorbell 2 (VCHIQ ARM -> VC) MB_DBell3 * &4c ; doorbell 3 MB_ChRd * &80 ; normal read - offset from MB_Base MB_ChWr * &a0 ; normal write MB_ChRWTop * &8c ; 4 word read or write MB_Pol * &90 ; NonPOP read MB_Snd * &94 ; sender read (bottom 2 bits) MB_Sta * &98 ; status read MB_Cnf * &9c ; config r/w ; ; mailbox register bits ; ; MB_Sta MB_Sta_Full * &80000000 ; mailbox full MB_Sta_Empty * &40000000 ; mailbox empty MB_Sta_Level * &000000ff ; mailbox content count ; MB_Cnf MB_Cnf_HDIrqEn * &00000001 ; mailbox has-data irq enable MB_Cnf_HSIrqEn * &00000002 ; mailbox has-space irq enable MB_Cnf_OpIrqEn * &00000004 ; mailbox Opp irq en MB_Cnf_MBClr * &00000008 ; write 1 then 0 to clear mailbox MB_Cnf_HDIrq * &00000010 ; mailbox has-data irq pending MB_Cnf_HSIrq * &00000020 ; mailbox has-space irq pending MB_Cnf_OpIrq * &00000040 ; mailbox Opp irq pending ; these flags are reset on any write to this register MB_Cnf_ErNone * &00000100 ; none read error MB_Cnf_ErWFull * &00000200 ; Write to full mailbox MB_Cnf_ErREmty * &00000400 ; read from empty mailbox ; mem barrier operation; ensures all explicit mem operations completed before ; instruction exits. ; (value 4 is all instructions, value 5 is just mem instructions) ; zeroes $r MACRO $label DataSyncBarrier $r, $cond $label MOV$cond $r, #0 [ {UAL} MCR$cond p15, #0, $r, c7, c10, #4 | MCR$cond p15, 0, $r, c7, c10,4 ] MEND MACRO $label DoMemBarrier $r, $cond $label MOV$cond $r, #0 [ {UAL} MCR$cond p15, #0, $r, c7, c10, #5 | MCR$cond p15, 0, $r, c7, c10,5 ] MEND MACRO $label FlushDataCacheV6 $tmp $label MOV $tmp, #0 MCR p15, 0, $tmp, c7, c14, 0 ; clean and invalidate entire data cache MEND MACRO $label FlushDataCacheV7 $clidr, $loc, $level, $ccsidr, $linelen, $way, $wayshift, $set, $tmp $label MRC p15, 1, $clidr, c0, c0, 1 ; read CLIDR ANDS $loc, $clidr, #&07000000 MOV $loc, $loc, LSR #23 ; extract level of coherence * 2 BEQ %F99 ; nothing to do if loc = 0 MOV $level, #0 ; cache level * 2 10 ADD $tmp, $level, $level, LSR #1 ; cache level * 3 MOV $tmp, $clidr, LSR $tmp AND $tmp, $tmp, #7 CMP $tmp, #2 BLT %FT40 ; no cache or only instruction cache at this level MCR p15, 2, $level, c0, c0, 0 ; write CSSELR ISB ; sync the change to the CCSIDR MRC p15, 1, $ccsidr, c0, c0, 0 ; read current CCSIDR AND $linelen, $ccsidr, #7 ; extract the line length field ADD $linelen, $linelen, #4 ; add 4 for the line length offset (log2 16 bytes) UBFX $way, $ccsidr, #3, #10 ; associativity aka number of ways CLZ $wayshift, $way 20 UBFX $set, $ccsidr, #13, #15 ; number of sets 30 ORR $tmp, $level, $way, LSL $wayshift ORR $tmp, $tmp, $set, LSL $linelen MCR p15, 0, $tmp, c7, c14, 2 ; data cache clean and invalidate by set/way SUBS $set, $set, #1 BGE %BT30 SUBS $way, $way, #1 BGE %BT20 DSB ; Cortex-A7 errata 814220: DSB required when changing cache levels when using set/way operations. This also counts as our end-of-maintenance DSB. 40 ADD $level, $level, #2 CMP $level, $loc BLT %BT10 99 MEND MACRO $label FlushDataCache $label CPUDetect lr BCS %FA07 FlushDataCacheV6 lr B %FT99 07 STMFD r13!, {r4-r9} FlushDataCacheV7 r2,r3,r4,r5,r6,r7,r8,r9,lr LDMFD r13!, {r4-r9} 99 MEND MACRO $label FlushDataCacheRange $startaddr,$endaddr,$cond $label BIC$cond $startaddr, $startaddr, #&1f BIC$cond $endaddr, $endaddr, #&1f [ {UAL} MCRR$cond p15, #0, $endaddr, $startaddr, c14 | MCRR$cond p15, 0, $endaddr, $startaddr, c14 ] MEND ; Board revision values (pre Pi 2), enumerated scheme ; Ref: https://www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/README.md BoardRevision_AorB256_First * &2 ; } Either an A or B BoardRevision_AorB256_Last * &9 ; } various manufacturers BoardRevision_AorB512_First * &D ; } Either an A or B BoardRevision_AorB512_Last * &F ; } various manufacturers BoardRevision_AorB_First * &2 ; } Either an A or B, 256MB or 512MB BoardRevision_AorB_Last * &F ; } and various manufacturers BoardRevision_BPlus_Sony * &10 ; Significant board revisions BoardRevision_Compute_Sony * &11 BoardRevision_APlus_Sony * &12 BoardRevision_BPlus_Embest * &13 BoardRevision_Compute_Embest * &14 BoardRevision_APlus_Embest * &15 ; Board revision values (Pi 2 and later), bitfield scheme BoardRevision_User_Shift * 24 BoardRevision_User_Mask * 255 :SHL: BoardRevision_User_Shift BoardRevision_Warranty * 1 :SHL: 25 ; if set, warranty void (Pi 2 and later) BoardRevision_WarrantyOld * 1 :SHL: 24 ; if set, warranty void (pre Pi 2) BoardRevision_NewScheme * 1 :SHL: 23 ; if set, indicates the following are in use BoardRevision_Mem_Shift * 20 BoardRevision_Mem_Mask * 7 :SHL: BoardRevision_Mem_Shift BoardRevision_Mem_256M * 0 :SHL: BoardRevision_Mem_Shift BoardRevision_Mem_512M * 1 :SHL: BoardRevision_Mem_Shift BoardRevision_Mem_1G * 2 :SHL: BoardRevision_Mem_Shift BoardRevision_Mem_2G * 3 :SHL: BoardRevision_Mem_Shift BoardRevision_Mem_4G * 4 :SHL: BoardRevision_Mem_Shift BoardRevision_Mem_8G * 5 :SHL: BoardRevision_Mem_Shift BoardRevision_Manuf_Shift * 16 BoardRevision_Manuf_Mask * 15 :SHL: BoardRevision_Manuf_Shift BoardRevision_Manuf_Sony * 0 :SHL: BoardRevision_Manuf_Shift BoardRevision_Manuf_Egoman * 1 :SHL: BoardRevision_Manuf_Shift BoardRevision_Manuf_Embest * 2 :SHL: BoardRevision_Manuf_Shift BoardRevision_Manuf_SonyJP * 3 :SHL: BoardRevision_Manuf_Shift BoardRevision_Manuf_Embest2 * 4 :SHL: BoardRevision_Manuf_Shift BoardRevision_Manuf_Stadium * 5 :SHL: BoardRevision_Manuf_Shift BoardRevision_Proc_Shift * 12 BoardRevision_Proc_Mask * 15 :SHL: BoardRevision_Proc_Shift BoardRevision_Proc_2835 * 0 :SHL: BoardRevision_Proc_Shift BoardRevision_Proc_2836 * 1 :SHL: BoardRevision_Proc_Shift BoardRevision_Proc_2837 * 2 :SHL: BoardRevision_Proc_Shift BoardRevision_Proc_2838 * 3 :SHL: BoardRevision_Proc_Shift BoardRevision_Model_Shift * 4 BoardRevision_Model_Mask * 255 :SHL: BoardRevision_Model_Shift BoardRevision_Model_A * 0 :SHL: BoardRevision_Model_Shift BoardRevision_Model_B * 1 :SHL: BoardRevision_Model_Shift BoardRevision_Model_APlus * 2 :SHL: BoardRevision_Model_Shift BoardRevision_Model_BPlus * 3 :SHL: BoardRevision_Model_Shift BoardRevision_Model_B2 * 4 :SHL: BoardRevision_Model_Shift BoardRevision_Model_Compute * 6 :SHL: BoardRevision_Model_Shift BoardRevision_Model_B3 * 8 :SHL: BoardRevision_Model_Shift BoardRevision_Model_Zero * 9 :SHL: BoardRevision_Model_Shift BoardRevision_Model_Compute3 * 10 :SHL: BoardRevision_Model_Shift BoardRevision_Model_ZeroW * 12 :SHL: BoardRevision_Model_Shift BoardRevision_Model_B3Plus * 13 :SHL: BoardRevision_Model_Shift BoardRevision_Model_A3Plus * 14 :SHL: BoardRevision_Model_Shift BoardRevision_Model_Compute3Plus * 16 :SHL: BoardRevision_Model_Shift BoardRevision_Model_B4 * 17 :SHL: BoardRevision_Model_Shift BoardRevision_Model_400 * 19 :SHL: BoardRevision_Model_Shift BoardRevision_Model_Compute4 * 20 :SHL: BoardRevision_Model_Shift BoardRevision_Rev_Shift * 0 BoardRevision_Rev_Mask * 15 :SHL: BoardRevision_Rev_Shift ; GPIO register set GPIO_Base * &00200000 ; base offset of GPIO regs GPFSel0 * &0 ; function sel 0 GPFSel1 * &4 ; function sel 1 GPFSel2 * &8 ; function sel 2 GPFSel3 * &c ; function sel 3 GPFSel4 * &10 ; function sel 4 GPFSel5 * &14 ; function sel 5 GPSet0 * &1c ; GPIO Set 0 GPSet1 * &20 ; GPIO Set 1 GPClr0 * &28 ; GPIO Clear 0 GPClr1 * &2c ; GPIO Clear 1 GPLev0 * &34 ; GPIO Level 0 GPLev1 * &38 ; GPIO Level 1 GPPEDS0 * &40 ; GPIO Pin Event Detect Status 0 GPPEDS1 * &44 ; GPIO Pin Event Detect Status 1 GPREDE0 * &4c ; GPIO rising edge detect enable 0 GPREDE1 * &50 ; GPIO rising edge detect enable 1 GPFEDE0 * &58 ; GPIO falling edge detect enable 0 GPFEDE1 * &5c ; GPIO falling edge detect enable 1 GPHIDE0 * &64 ; GPIO High detect enable 0 GPHIDE1 * &68 ; GPIO High detect enable 1 GPLODE0 * &70 ; GPIO Low detect enable 0 GPLODE1 * &74 ; GPIO Low detect enable 1 GPAREDE0 * &7c ; GPIO Async rising edge detect enable 0 GPAREDE1 * &80 ; GPIO Async rising edge detect enable 1 GPAFEDE0 * &88 ; GPIO Async falling edge detect enable 0 GPAFEDE1 * &8c ; GPIO Async falling edge detect enable 1 GPPUPDEN * &94 ; GPIO PullUp PullDown Enable GPPUDCK0 * &98 ; GPIO PullUp PullDown Clock 0 GPPUDCK1 * &9c ; GPIO PullUp PullDown Clock 1 GPPUDCT0 * &e4 ; GPIO Pullup Pulldown Control 0 (BCM2711) GPPUDCT1 * &e8 ; GPIO Pullup Pulldown Control 1 (BCM2711) GPPUDCT2 * &ec ; GPIO Pullup Pulldown Control 2 (BCM2711) GPPUDCT3 * &f0 ; GPIO Pullup Pulldown Control 3 (BCM2711) ; Auxio peripherals ; MiniUart uses TXD1 and RXD1 ; txd1 is GPIO14 alt 5 (010) ; rxd1 is GPIO15 alt 5 ; rts1 is GPIO17 alt 5 AUXIO_Base * &00215000 ; base of auxio regs AUXIRQ * &0 ; IRQ status AUXEnables * &4 ; AUX enables AUXMUIO * &40 ; MiniUart IO data AUXMUIER * &44 ; MU int enable AUXMUIIR * &48 ; MU int identify AUXMULCR * &4c ; MU Line Control AUXMUMCR * &50 ; MU Modem Control AUXMULSR * &54 ; MU Line Status AUXMUMSR * &58 ; MU Control Status AUXMUSCRATCH * &5c ; MU Scratch reg AUXMUCNTL * &60 ; MU extra control AUXMUSTAT * &64 ; MU extra status AUXMUBAUD * &68 ; MU Baud rate AUXSPI0 * &80 ; Aux SPI0 (aka SPI1) base AUXSPI1 * &C0 ; Aux SPI1 (aka SPI2) base AUXSPICNTL0 * &0 ; Aux API control 0 AUXSPICNTL1 * &4 ; Aux SPI control 1 AUXSPISTAT * &8 ; Aux API status AUXSPIIO * &10 ; Aux API data AUXSPIPEEK * &14 ; Aux SPI PEEK ; UART TXD0 RXD0 ; txd0 is GPIO14 alt 0 (100) ; rxd0 is GPIO15 alt 0 UART_Base * &00201000 ; base of uart regs UART1_offset * &00004000 ; offset to base of uart1 regs ; mini uart (above) UARTDR * &0 ; data reg UARTRSRECR * &4 ; UARTFLAG * &18 ; UARTIBRD * &24 ; int baud reg UARTFBRD * &28 ; fract baud reg UARTLCRH * &2c ; Line Control UARTCR * &30 ; Control Reg UARTIFLS * &34 ; Int FIFO Level UARTIMSC * &38 ; Int Mask set clear UARTRIS * &3c ; raw int status UARTMIS * &40 ; masked int status UARTICR * &44 ; irq clr UARTDMACR * &40 ; DMA Control UARTITCR * &80 ; test control UARTITIP * &84 ; integr test ip UARTITOP * &88 ; integ test op UARTTDR * &8c ; test data reg ; GPU System Timer Timer_Base * &00003000 ; base of system timer regs ST_CS * &00 ; control/status ST_CLO * &04 ; counter low ST_CHI * &08 ; counter high ST_C0 * &0C ; compare 0 ST_C1 * &10 ; compare 1 ST_C2 * &14 ; compare 2 ST_C3 * &18 ; compare 3 ; ARM Timer ARM_Timer_Base * &0000b400 ; base of ARM timer regs ; DMA registers DMA_Base * &00007000 DMA_CH_Count * 15 ; 16 channels, but one permanently reserved for GPU ; Message-based parallel host interface MPHI_Base * &00006000 ; Power management PM_Base * &00100000 ; power management PM_Password * &5a000000 ; for writes to be accepted PM_GNRIC * &00 PM_AUDIO * &04 PM_STATUS * &18 PM_RSTC * &1c ; reset control reg PM_RSTS * &20 ; reset status reg PM_WDOG * &24 ; watchdog control reg ; register bits PM_RSTC_DRCFG_MASK * &00000003 PM_RSTC_WRCFG_MASK * &00000030 PM_RSTC_WRCFG_FULLRST * &00000020 PM_RSTC_SRCFG_MASK * &00000300 PM_RSTC_QRCFG_MASK * &00003000 PM_RSTC_FRCFG_MASK * &00030000 PM_RSTC_HRCFG_MASK * &00300000 PM_RSTS_HADDRQ * 1:SHL:0 PM_RSTS_HADDRF * 1:SHL:1 PM_RSTS_HADDRH * 1:SHL:2 PM_RSTS_HADWRQ * 1:SHL:4 PM_RSTS_HADWRF * 1:SHL:5 PM_RSTS_HADWRH * 1:SHL:6 PM_RSTS_HADSRQ * 1:SHL:8 PM_RSTS_HADSRF * 1:SHL:9 PM_RSTS_HADSRH * 1:SHL:10 PM_RSTS_HADPOR * 1:SHL:12 PM_WDOG_TIME_MASK * &000fffff ; ; USB_Base * &00980000 ; USB ISP_Base * &00a00000 ; ISP ; ; Interrupt handling ; IRQ_Base * &0000B200 IRQ_PENDB * &00 ; read: pending basic interrupts (devices 64-95) IRQ_PEND1 * &04 ; read: pending interrupts 1 (GPU IRQs 0-31, devices 0-31) IRQ_PEND2 * &08 ; read: pending interrupts 2 (GPU IRQs 32-63, devices 32-63) ; In BCM2838, IRQ_PEND* have shuffled round to match the order of the other registers! IRQ_PEND1_BCM2838 * &00 ; read: pending interrupts 1 (GPU IRQs 0-31, devices 0-31) IRQ_PEND2_BCM2838 * &04 ; read: pending interrupts 2 (GPU IRQs 32-63, devices 32-63) IRQ_PENDB_BCM2838 * &08 ; read: pending basic interrupts (devices 64-95) IRQ_FIQCTL * &0C ; FIQ control register - not on BCM2838 IRQ_EN1 * &10 ; read: enabled interrupts 1; write: bits to OR into enabled interrupts 1 IRQ_EN2 * &14 ; read: enabled interrupts 2; write: bits to OR into enabled interrupts 2 IRQ_ENB * &18 ; read: enabled basic interrupts; write: bits to OR into enabled basic interrupts IRQ_DIS1 * &1C ; read: enabled interrupts 1; write: bits to BIC from enabled interrupts 1 IRQ_DIS2 * &20 ; read: enabled interrupts 2; write: bits to BIC from enabled interrupts 2 IRQ_DISB * &24 ; read: enabled basic interrupts; write: bits to BIC from enabled basic interrupts ; In BCM2838, IRQ_DIS* move along by 4 bytes! IRQ_DIS1_BCM2838 * &20 ; read: enabled interrupts 1; write: bits to BIC from enabled interrupts 1 IRQ_DIS2_BCM2838 * &24 ; read: enabled interrupts 2; write: bits to BIC from enabled interrupts 2 IRQ_DISB_BCM2838 * &28 ; read: enabled basic interrupts; write: bits to BIC from enabled basic interrupts ; ; FIQ handling (BCM2838 only) ; FIQ_Base * &0000B300 FIQ_PEND1 * &00 ; read: pending interrupts 1 (GPU IRQs 0-31, devices 0-31) FIQ_PEND2 * &04 ; read: pending interrupts 2 (GPU IRQs 32-63, devices 32-63) FIQ_PENDB * &08 ; read: pending basic interrupts (devices 64-95) FIQ_EN1 * &10 ; read: enabled interrupts 1; write: bits to OR into enabled interrupts 1 FIQ_EN2 * &14 ; read: enabled interrupts 2; write: bits to OR into enabled interrupts 2 FIQ_ENB * &18 ; read: enabled basic interrupts; write: bits to OR into enabled basic interrupts FIQ_DIS1 * &20 ; read: enabled interrupts 1; write: bits to BIC from enabled interrupts 1 FIQ_DIS2 * &24 ; read: enabled interrupts 2; write: bits to BIC from enabled interrupts 2 FIQ_DISB * &28 ; read: enabled basic interrupts; write: bits to BIC from enabled basic interrupts ; ; Extended interrupt demultiplexing (BCM2838 only) ; ExtIRQ_Base * &0000F300 ExtIRQ_STATUS0 * &00 ; read: pending extended interrupts 0-31 ExtIRQ_STATUS1 * &04 ; read: pending extended interrupts 32-51 ExtIRQ_MASK_STATUS0 * &08 ; read: masked extended interrupts 0-31 ExtIRQ_MASK_STATUS1 * &0C ; read: masked extended interrupts 32-51 ExtIRQ_MASK_SET0 * &08 ; write: set mask for extended interrupts 0-31 ExtIRQ_MASK_SET1 * &0C ; write: set mask for extended interrupts 32-51 ExtIRQ_MASK_CLEAR0 * &08 ; write: clear mask for extended interrupts 0-31 ExtIRQ_MASK_CLEAR1 * &0C ; write: clear mask for extended interrupts 32-51 ; Raspberry Pi interrupt sources. ; There are 5 groups of interrupt sources: ; * 64 GPU interrupts. ; * On BCM2835-7, these are mapped to bits in the "1" and "2" registers, but ; some are also mapped into the upper 24 bits of the "base" interrupt ; registers. We don't use the upper bits of the "base" registers because ; masking is only possible in the "1" and "2" registers, because IRQ_FIQCTL ; also (and only) accepts sources in that order, and because it keeps the ; timers with the lowest priority, which is desirable because we run our ; counter from them. ; * BCM2838 has the same interrupt controller block, but it is normally ; disabled in favour of the GICv2, which features additional important ; interrupt sources. With the GIC, the GPU interrupts are mapped to SPIs ; 64 to 127. ; * 8 ARM interrupts. ; * On BCM2835-7, these are mapped into the bottom 8 bits of the "base" ; interrupt registers. ; * On the BCM2838 GIC, they're mapped to SPIs 32-39. ; * 32 core-specific interrupts managed by the QA7 block in BCM2836-8. ; * These are at least partially mapped to GIC SPIs 0-31, in a non-trivial ; manner. ; * 64 GPU extended peripheral interrupts in BCM2838. These are routed through ; GPU interrupt 58 when bypassing the GIC, otherwise they're mapped to SPIs ; 128-191. ; * The GIC also has some extra BCM2838-specific interrupts mapped to SPIs ; 40-63 (and potentially some other locations). It's unclear whether these ; are accessible when the GIC is bypassed. ; devices in register 1 - start at 0 iDev_GPU_Timer0 * 0 ; not on list in datasheet iDev_GPU_Timer1 * 1 ; not on list in datasheet iDev_GPU_Timer2 * 2 ; not on list in datasheet iDev_GPU_Timer3 * 3 ; not on list in datasheet iDev_GPU_Codec0 * 4 ; not on list in datasheet iDev_GPU_Codec1 * 5 ; not on list in datasheet iDev_GPU_Codec2 * 6 ; not on list in datasheet iDev_GPU_VCJPEG * 7 ; not on list in datasheet iDev_GPU_ISP * 8 ; not on list in datasheet iDev_GPU_VCUSB * 9 ; not on list in datasheet iDev_GPU_VC3D * 10 ; not on list in datasheet iDev_GPU_Transp * 11 ; not on list in datasheet iDev_GPU_MCSync0 * 12 ; not on list in datasheet iDev_GPU_MCSync1 * 13 ; not on list in datasheet iDev_GPU_MCSync2 * 14 ; not on list in datasheet iDev_GPU_MCSync3 * 15 ; not on list in datasheet iDev_GPU_DMA0 * 16 ; not on list in datasheet iDev_GPU_DMA1 * 17 ; not on list in datasheet iDev_GPU_VCDMA2 * 18 ; not on list in datasheet iDev_GPU_VCDMA3 * 19 ; not on list in datasheet iDev_GPU_DMA4 * 20 ; not on list in datasheet iDev_GPU_DMA5 * 21 ; not on list in datasheet iDev_GPU_DMA6 * 22 ; not on list in datasheet iDev_GPU_DMA7 * 23 ; not on list in datasheet; BCM2835-7 iDev_GPU_DMA7_8 * 23 ; channels 7 & 8 use shared interrupt on BCM2838 iDev_GPU_DMA8 * 24 ; not on list in datasheet; BCM2835-7 iDev_GPU_DMA9_10 * 24 ; channels 9 & 10 use shared interrupt on BCM2838 iDev_GPU_DMA9 * 25 ; not on list in datasheet; BCM2835-7 iDev_GPU_DMA40_0 * 25 ; BCM2838 iDev_GPU_DMA10 * 26 ; not on list in datasheet; BCM2835-7 iDev_GPU_DMA40_1 * 26 ; BCM2838 iDev_GPU_DMA11_14 * 27 ; channels 11-14 shared IRQ, BCM2835-7 iDev_GPU_DMA40_2 * 27 ; BCM2838 iDev_GPU_DMA * 28 ; "unused shared IRQ for all channels", BCM2835-7 iDev_GPU_DMA40_3 * 28 ; BCM2838 iDev_GPU_AuxInt * 29 ; shared SPI1, SPI2, UART1 iDev_GPU_ARM * 30 ; not on list in datasheet iDev_GPU_VPUDMA * 31 ; not on list in datasheet ; devices in register 2 - start at 32 iDev_GPU_HostPort * 32 ; not on list in datasheet iDev_GPU_VidScale * 33 ; not on list in datasheet iDev_GPU_CCP2TX * 34 ; not on list in datasheet iDev_GPU_ArgonLocalIntC * 34 ; BCM2838 iDev_GPU_SDC * 35 ; not on list in datasheet iDev_GPU_DSI0 * 36 ; not on list in datasheet iDev_GPU_AVE * 37 ; not on list in datasheet iDev_GPU_Cam0 * 38 ; not on list in datasheet iDev_GPU_Cam1 * 39 ; not on list in datasheet iDev_GPU_HDMI0 * 40 ; not on list in datasheet iDev_GPU_HDMI1 * 41 ; not on list in datasheet iDev_GPU_PixVal1 * 42 ; not on list in datasheet iDev_GPU_I2CSPISlv * 43 iDev_GPU_DSI1 * 44 ; not on list in datasheet iDev_GPU_PWA0 * 45 ; PixelValve on BCM2838 iDev_GPU_PWA1 * 46 ; PixelValve on BCM2838 iDev_GPU_CPR * 47 ; not on list in datasheet iDev_GPU_SMI * 48 ; also FirmwareKMS iDev_GPU_GPIO0 * 49 iDev_GPU_GPIO1 * 50 iDev_GPU_GPIO2 * 51 iDev_GPU_GPIO3 * 52 iDev_GPU_I2C * 53 ; shared I2C0-I2C2 on BCM2835-7; shared I2C0-I2C6 on BCM2838 iDev_GPU_SPI * 54 ; SPI0 on BCM2835-7; shared SPI0, SPI3-SPI6 on BCM2838 iDev_GPU_PCM * 55 iDev_GPU_SDIO * 56 ; not on list in datasheet; only controller on BCM235-7; backward-compatible controller on BCM2838 iDev_GPU_Uart * 57 ; UART0 on BCM2835-7; shared UART0, UART2-5 on BCM2838 iDev_GPU_SlimBus * 58 ; not on list in datasheet iDev_GPU_Extended * 58 ; extended peripheral interrupts all routed through here on BCM2838 when not using GIC iDev_GPU_Vec * 59 ; not on list in datasheet iDev_GPU_CPG * 60 ; not on list in datasheet iDev_GPU_RNG * 61 ; not on list in datasheet iDev_GPU_VCSDIO * 62 ; not on list in datasheet; fast controller on BCM2838 iDev_GPU_AVSPMON * 63 ; not on list in datasheet iDev_ARM_Timer * 64+0 iDev_ARM_Mbx * 64+1 iDev_ARM_DBell0 * 64+2 iDev_ARM_DBell1 * 64+3 iDev_ARM_GPU0Hlt * 64+4 iDev_ARM_GPU1Hlt * 64+5 iDev_ARM_IllegAcs1 * 64+6 iDev_ARM_IllegAcs0 * 64+7 ; Following iDev_ARM interrupts aren't valid when using the GIC (GIC reuses some for different purposes) iDev_ARM_MiscGPU1 * 64+8 ; OR of GPU IRQs 0-31 excluding those listed below iDev_ARM_MiscGPU2 * 64+9 ; OR of GPU IRQs 32-63 excluding those listed below iDev_ARM_VCJPEG * 64+10 ; copy of GPU IRQ 7 iDev_ARM_VCUSB * 64+11 ; copy of GPU IRQ 9 iDev_ARM_VC3D * 64+12 ; copy of GPU IRQ 10 iDev_ARM_VCDMA2 * 64+13 ; copy of GPU IRQ 18 iDev_ARM_VCDMA3 * 64+14 ; copy of GPU IRQ 19 iDev_ARM_I2C * 64+15 ; copy of GPU IRQ 53 iDev_ARM_SPI * 64+16 ; copy of GPU IRQ 54 iDev_ARM_PCM * 64+17 ; copy of GPU IRQ 55 iDev_ARM_SDIO * 64+18 ; copy of GPU IRQ 56 iDev_ARM_Uart * 64+19 ; copy of GPU IRQ 57 iDev_ARM_VCSDIO * 64+20 ; copy of GPU IRQ 62 iDev_ARM11_Max * 64+21 ; Extra interrupt sources for QA7 ; These are all core-specific interrupts ; Note that the original interrupts (0 - iDev_ARM11_Max) can only be routed to ; one core at a time (although IRQ and FIQ can be routed differently if we ; desire). If iDev_QA7_GPU is firing, it indicates that we are the owner of the ; GPU interrupts and should check its status registers to determine the source. iDev_QA7_Base * iDev_ARM11_Max ^ iDev_QA7_Base iDev_QA7_CNTPSIRQ # 4 ; Core-specific iDev_QA7_CNTPNSIRQ # 4 ; Core-specific iDev_QA7_CNTPHPIRQ # 4 ; Core-specific iDev_QA7_CNTPVIRQ # 4 ; Core-specific iDev_QA7_MBox0 # 4 ; Core-specific iDev_QA7_MBox1 # 4 ; Core-specific iDev_QA7_MBox2 # 4 ; Core-specific iDev_QA7_MBox3 # 4 ; Core-specific iDev_QA7_GPU # 4 ; Each of IRQ+FIQ can only be assigned to one core at a time iDev_QA7_PMU # 4 ; Core-specific iDev_QA7_AXI # 4 ; Can only be IRQ of core 0 iDev_QA7_LocalTimer # 4 ; Can only be assigned to one core (as either IRQ or FIQ) iDev_QA7_Max # 0 ; GPU extended peripheral interrupt sources - overlaid on QA7 interrupts to ; avoid wasting lots of number space (extended interrupts are only used when ; the GIC is used, which also mostly rules out QA7 interrupts) iDev_Ext_Base * 64+32 iDev_Ext_Vec * iDev_Ext_Base+0 iDev_Ext_BVNB0 * iDev_Ext_Base+1 iDev_Ext_BVNF0 * iDev_Ext_Base+2 iDev_Ext_BVNF1 * iDev_Ext_Base+3 iDev_Ext_BVNF5 * iDev_Ext_Base+4 iDev_Ext_BVNF9 * iDev_Ext_Base+5 iDev_Ext_BVNF16 * iDev_Ext_Base+6 iDev_Ext_BVNM0 * iDev_Ext_Base+7 iDev_Ext_BVNB1 * iDev_Ext_Base+8 iDev_Ext_AVS * iDev_Ext_Base+9 ; used (for thermal) by Linux iDev_Ext_HDMI0_TX * iDev_Ext_Base+10 iDev_Ext_HDMI1_TX * iDev_Ext_Base+11 iDev_Ext_HDMI_AON_TX * iDev_Ext_Base+12 iDev_Ext_HDMI_BSC_TX * iDev_Ext_Base+13 iDev_Ext_PCIe_Err_Attn * iDev_Ext_Base+14 iDev_Ext_PCIe_IntA * iDev_Ext_Base+15 ; used by Linux iDev_Ext_PCIe_IntB * iDev_Ext_Base+16 ; used by Linux iDev_Ext_PCIe_IntC * iDev_Ext_Base+17 ; used by Linux iDev_Ext_PCIe_IntD * iDev_Ext_Base+18 ; used by Linux iDev_Ext_PCIe_IntR * iDev_Ext_Base+19 iDev_Ext_PCIe_MSI * iDev_Ext_Base+20 ; used by Linux iDev_Ext_PCIe_NMI * iDev_Ext_Base+21 iDev_Ext_HVD0 * iDev_Ext_Base+22 iDev_Ext_MEMC0 * iDev_Ext_Base+23 iDev_Ext_SATA_AHCI * iDev_Ext_Base+24 iDev_Ext_SATA_GRB * iDev_Ext_Base+25 iDev_Ext_Sys * iDev_Ext_Base+26 iDev_Ext_Upg_Main * iDev_Ext_Base+27 iDev_Ext_V3D * iDev_Ext_Base+28 iDev_Ext_Genet_A * iDev_Ext_Base+29 ; used by Linux iDev_Ext_Genet_B * iDev_Ext_Base+30 ; used by Linux iDev_Ext_BVNM1 * iDev_Ext_Base+31 ; Note: 32+ aren't accessible via the GIC (boot stub doesn't assign them to the correct group) iDev_Ext_HDMI_SEC * iDev_Ext_Base+32 iDev_Ext_CPU * iDev_Ext_Base+33 iDev_Ext_AIO * iDev_Ext_Base+34 iDev_Ext_DTE_Int0 * iDev_Ext_Base+35 iDev_Ext_DTE_Int1 * iDev_Ext_Base+36 iDev_Ext_DTE_Int2 * iDev_Ext_Base+37 iDev_Ext_Upg_Tmr * iDev_Ext_Base+38 iDev_Ext_GFX * iDev_Ext_Base+39 iDev_Ext_CPU_Therm_Hi * iDev_Ext_Base+40 iDev_Ext_XPT_RAV * iDev_Ext_Base+41 iDev_Ext_XPT_MCPB * iDev_Ext_Base+42 iDev_Ext_XPT_FE * iDev_Ext_Base+43 iDev_Ext_XPT_PCR * iDev_Ext_Base+44 iDev_Ext_XPT_CPU_Status * iDev_Ext_Base+45 iDev_Ext_XPT_SCPU_Status * iDev_Ext_Base+46 iDev_Ext_XPT_SCPU_RAV * iDev_Ext_Base+47 iDev_Ext_USB0_XHCI_0 * iDev_Ext_Base+48 ; used by Linux iDev_Ext_USB0_USBD * iDev_Ext_Base+49 iDev_Ext_USB0_PP_Changed_0 * iDev_Ext_Base+50 iDev_Ext_Max * iDev_Ext_Base+51 ; Remaining GIC interrupt sources iDev_GIC_Base * iDev_Ext_Base+64 iDev_GIC_QA7_Core0_MBox0 * iDev_GIC_Base+0 ; Mailboxes from the QA7 block iDev_GIC_QA7_Core0_MBox1 * iDev_GIC_Base+1 ; iDev_GIC_QA7_Core0_MBox2 * iDev_GIC_Base+2 ; Note that we don't attempt to iDev_GIC_QA7_Core0_MBox3 * iDev_GIC_Base+3 ; map these device numbers to iDev_GIC_QA7_Core1_MBox0 * iDev_GIC_Base+4 ; their iDev_QA7 equivalents - it iDev_GIC_QA7_Core1_MBox1 * iDev_GIC_Base+5 ; would add a bit too much iDev_GIC_QA7_Core1_MBox2 * iDev_GIC_Base+6 ; complexity to the interrupt iDev_GIC_QA7_Core1_MBox3 * iDev_GIC_Base+7 ; handling. Instead we just have iDev_GIC_QA7_Core2_MBox0 * iDev_GIC_Base+8 ; the HAL report the different iDev_GIC_QA7_Core2_MBox1 * iDev_GIC_Base+9 ; device numbers to the OS. iDev_GIC_QA7_Core2_MBox2 * iDev_GIC_Base+10 iDev_GIC_QA7_Core2_MBox3 * iDev_GIC_Base+11 iDev_GIC_QA7_Core3_MBox0 * iDev_GIC_Base+12 iDev_GIC_QA7_Core3_MBox1 * iDev_GIC_Base+13 iDev_GIC_QA7_Core3_MBox2 * iDev_GIC_Base+14 iDev_GIC_QA7_Core3_MBox3 * iDev_GIC_Base+15 iDev_GIC_PMU0 * iDev_GIC_Base+16 iDev_GIC_PMU1 * iDev_GIC_Base+17 iDev_GIC_PMU2 * iDev_GIC_Base+18 iDev_GIC_PMU3 * iDev_GIC_Base+19 iDev_GIC_VCUSB * iDev_ARM_MiscGPU1 ; GIC SPI 40, additional interrupt for DWC ;IIC0 (BSC0, i.e. Broadcom Serial Controller 0) IIC_Base0 * &00205000 ; base of IIC0 ;IIC1 (BCS1, i.e. Broadcom Serial Controller 1) IIC_Base1 * &00804000 IIC_C * &00 ; Control IIC_S * &04 ; Status IIC_DLEN * &08 ; Data Length IIC_A * &0C ; Slave Address IIC_FIFO * &10 ; Data FIFO IIC_DIV * &14 ; Clock Divider IIC_DEL * &18 ; Data Delay IIC_CLKT * &1C ; Clock Stretch Timeout ; The peripherals (including the local interrupt controller) introduced with ; the Quad Cortex-A7, and the GIC (in BCM2838) share an IO region. INT_BASE_BCM2836 * &40000000 INT_BASE_BCM2838 * &FF800000 INT_SIZE * &800000 ; When accessing by virtual address, the following are relative to IntBase ; ARM control registers for quad core chips (BCM2836, BCM2837, etc.) ; ref: https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2836/QA7_rev3.4.pdf QA7_CONTROL * &0000 QA7_CORE_TIMER_PRESCALE * &0008 QA7_GPU_INT_ROUTING * &000C QA7_PMU_INT_ROUT_SET * &0010 QA7_PMU_INT_ROUT_CLR * &0014 QA7_CORE_TIMER_LSW * &001C QA7_CORE_TIMER_MSW * &0020 QA7_LOCAL_INT_ROUTING * &0024 QA7_AXI_OUTSTANDING_CNT * &002C QA7_AXI_OUTSTANDING_IRQ * &0030 QA7_LOCAL_TIMER_CTRL_STAT * &0034 QA7_LOCAL_TIMER_WRFLAGS * &0038 QA7_CORE0_TIMER_INT_CTRL * &0040 QA7_CORE1_TIMER_INT_CTRL * &0044 QA7_CORE2_TIMER_INT_CTRL * &0048 QA7_CORE3_TIMER_INT_CTRL * &004C QA7_CORE0_MBOX_INT_CTRL * &0050 QA7_CORE1_MBOX_INT_CTRL * &0054 QA7_CORE2_MBOX_INT_CTRL * &0058 QA7_CORE3_MBOX_INT_CTRL * &005C QA7_CORE0_IRQ_SOURCE * &0060 QA7_CORE1_IRQ_SOURCE * &0064 QA7_CORE2_IRQ_SOURCE * &0068 QA7_CORE3_IRQ_SOURCE * &006C QA7_CORE0_FIQ_SOURCE * &0070 QA7_CORE1_FIQ_SOURCE * &0074 QA7_CORE2_FIQ_SOURCE * &0078 QA7_CORE3_FIQ_SOURCE * &007C QA7_CORE0_MBOX0_SET * &0080 ; Write to set bits in mailbox QA7_CORE0_MBOX1_SET * &0084 QA7_CORE0_MBOX2_SET * &0088 QA7_CORE0_MBOX3_SET * &008C QA7_CORE1_MBOX0_SET * &0090 QA7_CORE1_MBOX1_SET * &0094 QA7_CORE1_MBOX2_SET * &0098 QA7_CORE1_MBOX3_SET * &009C QA7_CORE2_MBOX0_SET * &00A0 QA7_CORE2_MBOX1_SET * &00A4 QA7_CORE2_MBOX2_SET * &00A8 QA7_CORE2_MBOX3_SET * &00AC QA7_CORE3_MBOX0_SET * &00B0 QA7_CORE3_MBOX1_SET * &00B4 QA7_CORE3_MBOX2_SET * &00B8 QA7_CORE3_MBOX3_SET * &00BC QA7_CORE0_MBOX0_RDCLR * &00C0 ; Write to clear bits in mailbox QA7_CORE0_MBOX1_RDCLR * &00C4 QA7_CORE0_MBOX2_RDCLR * &00C8 QA7_CORE0_MBOX3_RDCLR * &00CC QA7_CORE1_MBOX0_RDCLR * &00D0 QA7_CORE1_MBOX1_RDCLR * &00D4 QA7_CORE1_MBOX2_RDCLR * &00D8 QA7_CORE1_MBOX3_RDCLR * &00DC QA7_CORE2_MBOX0_RDCLR * &00E0 QA7_CORE2_MBOX1_RDCLR * &00E4 QA7_CORE2_MBOX2_RDCLR * &00E8 QA7_CORE2_MBOX3_RDCLR * &00EC QA7_CORE3_MBOX0_RDCLR * &00F0 QA7_CORE3_MBOX1_RDCLR * &00F4 QA7_CORE3_MBOX2_RDCLR * &00F8 QA7_CORE3_MBOX3_RDCLR * &00FC ; GIC (added at Pi 4) GICD_Base * &00041000 GICD_CTLR * &000 GICD_TYPER * &004 GICD_IIDR * &008 GICD_IGROUPR * &080 GICD_ISENABLER * &100 GICD_ICENABLER * &180 GICD_ISPENDR * &200 GICD_ICPENDR * &280 GICD_ISACTIVER * &300 GICD_ICACTIVER * &380 GICD_IPRIORITYR * &400 GICD_ITARGETSR * &800 GICD_ICFGR * &C00 GICD_PPISR * &D00 GICD_SPISR * &D04 GICD_SGIR * &F00 GICD_CPENDSGIR * &F10 GICD_SPENDSGIR * &F20 GICD_PIDR4 * &FD0 GICD_PIDR5 * &FD4 GICD_PIDR6 * &FD8 GICD_PIDR7 * &FDC GICD_PIDR0 * &FE0 GICD_PIDR1 * &FE4 GICD_PIDR2 * &FE8 GICD_PIDR3 * &FEC GICD_CIDR0 * &FF0 GICD_CIDR1 * &FF4 GICD_CIDR2 * &FF8 GICD_CIDR3 * &FFC GICC_Base * &00042000 GICC_CTLR * &0000 GICC_PMR * &0004 GICC_BPR * &0008 GICC_IAR * &000C GICC_EOIR * &0010 GICC_RPR * &0014 GICC_HPPIR * &0018 GICC_ABPR * &001C GICC_AIAR * &0020 GICC_AEOIR * &0024 GICC_AHPPIR * &0028 GICC_APR0 * &00D0 GICC_NSAPR0 * &00E0 GICC_IIDR * &00FC GICC_DIR * &1000 ; The GIC virtual interfaces probably aren't interesting unless you're writing ; a hypervisor. ; Extra peripheral range added at Pi 4. These are all relative to PeriBase2 ; V3D V3D_Base * &00500000 ; PCIe PCIe_Base * &01500000 PCIe_BRIDGE_CFG * 0 ; Standard config space for the built-in bridge PCIe_MISC_CTRL * &4008 PCIe_MISC_CTRL_SCB_ACCESS_EN * 1:SHL:12 PCIe_MISC_CTRL_CFG_READ_SAFE * 1:SHL:13 PCIe_MISC_CTRL_MAX_BURST_SHIFT * 20 PCIe_MISC_CTRL_SCB0_SIZE_SHIFT * 27 ; 5b values PCIe_MISC_CTRL_SCB1_SIZE_SHIFT * 22 PCIe_MISC_CTRL_SCB2_SIZE_SHIFT * 0 PCIe_PCI_MEM_LO_WIN0 * &400C PCIe_PCI_MEM_HI_WIN0 * &4010 PCIe_PCI_MEM_LO_WIN1 * &4014 PCIe_PCI_MEM_HI_WIN1 * &4018 PCIe_PCI_MEM_LO_WIN2 * &401C PCIe_PCI_MEM_HI_WIN2 * &4020 PCIe_PCI_MEM_LO_WIN3 * &4024 PCIe_PCI_MEM_HI_WIN3 * &4028 PCIe_RC_CONFIG_LO_BAR1 * &402C ; For inbound memory PCIe_RC_CONFIG_HI_BAR1 * &4030 ; transfers PCI->GISB PCIe_RC_CONFIG_LO_BAR2 * &4034 ; For inbound memory PCIe_RC_CONFIG_HI_BAR2 * &4038 ; transfers PCI->CPU PCIe_RC_CONFIG_LO_BAR3 * &403C ; For inbound memory PCIe_RC_CONFIG_HI_BAR3 * &4040 ; transfers PCI->SCB PCIe_LINK_STATUS * &4068 PCIe_LINK_STATUS_PORT * 1:SHL:7 PCIe_LINK_STATUS_IN_L23 * 1:SHL:6 PCIe_LINK_STATUS_DOWNLINK_ACT * 1:SHL:5 PCIe_LINK_STATUS_PHYLINK_UP * 1:SHL:4 PCIe_CPU_MEM_BASE_LIMIT_WIN0 * &4070 PCIe_CPU_MEM_BASE_LIMIT_WIN1 * &4074 PCIe_CPU_MEM_BASE_LIMIT_WIN2 * &4078 PCIe_CPU_MEM_BASE_LIMIT_WIN3 * &407C PCIe_CPU_MEM_BASE_SHIFT * 4 PCIe_CPU_MEM_BASE_MASK * &FFF:SHL:PCIe_CPU_MEM_BASE_SHIFT PCIe_CPU_MEM_LIMIT_SHIFT * 20 PCIe_CPU_MEM_LIMIT_MASK * &FFF:SHL:PCIe_CPU_MEM_LIMIT_SHIFT PCIe_CPU_MEM_BASE_HI_WIN0 * &4080 PCIe_CPU_MEM_LIMIT_HI_WIN0 * &4084 PCIe_CPU_MEM_BASE_HI_WIN1 * &4088 PCIe_CPU_MEM_LIMIT_HI_WIN1 * &408C PCIe_CPU_MEM_BASE_HI_WIN2 * &4090 PCIe_CPU_MEM_LIMIT_HI_WIN2 * &4094 PCIe_CPU_MEM_BASE_HI_WIN3 * &4098 PCIe_CPU_MEMLIMIT_HI_WIN3 * &409C PCIe_INTR2_STATUS * &4300 PCIe_INTR2_SET * &4304 PCIe_INTR2_CLEAR * &4308 PCIe_INTR2_MASK * &430C PCIe_INTR2_MASK_SET * &4310 PCIe_INTR2_MASK_CLEAR * &4314 PCIe_EXT_CFG_DATA * &8000 ; Up to 4k of config space PCIe_EXT_CFG_INDEX * &9000 ; Config space selector PCIe_EXT_CFG_INDEX_BUS_SHIFT * 20 PCIe_EXT_CFG_INDEX_DEV_SHIFT * 15 PCIe_EXT_CFG_INDEX_FN_SHIFT * 12 PCIe_RGR1_SW_INIT1 * &9210 PCIe_RGR1_SW_INIT1_INIT * 1:SHL:1 PCIe_RGR1_SW_INIT1_RESET * 1:SHL:0 ; Gigabit Ethernet GENET_Base * &01580000 ; Thermal sensor Thermal_Base * &015d2200 ] END