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  1. 14 Nov, 2020 1 commit
    • Ben Avison's avatar
      Support new Pi models · 7f397181
      Ben Avison authored
      * Raspberry Pi 400: verified as booting to desktop.
      * Compute Module 3+: some changes to SD support to make it behave like the
        plain Compute Module 3 (previously it was falling into the model B+ code
        path and setting up GPIO in the expectation that an activity LED was
        attached, which is not a given for a Compute Module). Not tested.
      * Compute Module 4: tentative support added. Not tested. In particular, we
        don't know what the revision numbers will be yet, so the entries in
        `GPIO_Board_Conversion_Table` may not match real hardware.
      * SD subsystem now assumes any future models are similar to the Pi 4 and 400,
        and thus we're more likely that they will "just work" out of the box.
      
      Version 0.92. Tagged as 'HAL_BCM2835-0_92'
      7f397181
  2. 10 Oct, 2020 1 commit
  3. 01 Aug, 2020 1 commit
    • Robert Sprowson's avatar
      On Pi 4's with no VL805 firmware EEPROM, softload it · f84ef1c2
      Robert Sprowson authored
      Some Pi 4's - for example, the recently released 8GB variant - don't have the firmware EEPROM on the VL805 fitted. The VideoCore loads default firmware on power on in order to do USB booting, but when RISC OS takes over and does a PCI fundamental reset the VL805 ends up with no firmware running.
      Detect this (by peeking the firmware version) and use the NotifyXHCIReset mailbox message to cause the VideoCore to softload the firmware again. Earlier built PCBs *do* contain a firmware EEPROM and skip the mailbox message.
      
      By inspection with a prototype version in BASIC it appears the SCB access needs to be enabled for this to work, it previously wasn't, hence the extra PCI setup step.
      
      Also, reduce the PCI reset delay and rename PCIe_RGR1_SW_INIT1_POWERDOWN to more accurately reflect what it does.
      
      Version 0.89. Tagged as 'HAL_BCM2835-0_89'
      f84ef1c2
  4. 19 Jun, 2020 1 commit
    • Jeffrey Lee's avatar
      DMA improvements & fixes · c6f51390
      Jeffrey Lee authored
      * Update DMA & DMA lite channels to work on Pi 4 (HAL_IRQClear calls
      needed)
      * Fix DMAL_Abort / DMAL_Reset to reset the channel properly (register
      muddle meant the old reset code wasn't doing anything - and wasn't a
      particularly great way of resetting anyway)
      * Fix DMAL_CurtailListTransfer not working very well
      * Fix IRQ mapping of channels 11-14, allowing channels 12-14 to be used
      * Implement support for Pi 4 DMA4 channels. On Pi 4 these are the only
      channels we'll bother using, since DMA & DMA lite have annoying
      restrictions on accessing RAM above 1GB
      c6f51390
  5. 30 May, 2020 1 commit
    • David Pitt's avatar
      Update table for 4B revision 1.4 · 75c0e15f
      David Pitt authored
      Detail:
        The 8GB model has a new PCB revision too.
      Admin:
        Submission from David Pitt.
      
      Version 0.85. Tagged as 'HAL_BCM2835-0_85'
      75c0e15f
  6. 14 Mar, 2020 10 commits
    • Robert Sprowson's avatar
      Add remaining PCIe setup steps · ae6f7f27
      Robert Sprowson authored
      Memory window now enabled on the VIA VL805, on-chip bridge set to forward memory transactions, ARM CPU to PCI address space translated.
      Since we know there's only the VIA chip on the bus, there's no dynamic probing going on like platforms that have PCI sockets. Its BAR settings are derived from defines at the top of PCI.s, so to browse the XHCI capability registers just peek at
        *Memory p 600100000 +20
      Only 1 of the 4 address space translation windows is used.
      ae6f7f27
    • Robert Sprowson's avatar
      Add preliminary PCIe setup steps · 5acaaf41
      Robert Sprowson authored
      Just enough pokes to be able to scan configuration space such that the VIA XHCI controller can be seen by PCI Manager. Note: at present there are no memory or IO windows open, so you can't (yet) see XHCI registers.
      5acaaf41
    • Jeffrey Lee's avatar
      Add GIC interrupt controller support for BCM2838. · 288ddd47
      Jeffrey Lee authored
      * Requires 'enable_gic=1' in config.txt (or Pi4 dtb to be present?)
      * IRQs are managed via the GIC, FIQs via the BCM2838 FIQ controller
      * Implemented in s.IntVC6 to avoid making s.Interrupts too
      confusing.
      * Previous VC6 interrupt support removed from s.Interrupts
      * From the OS's perspective, interrupt numbers mostly remain
      unchanged. However iDev_QA7 interrupts are unavailable, and some of
      the BCM2838 interrupts have been overlaid ontop of them.
      * Device drivers must take care to issue HAL_IRQClear, as that is
      a new requirement for this HAL
      288ddd47
    • Ben Avison's avatar
      Support >1GB RAM · 9f19d29e
      Ben Avison authored
      RAM sizes above 1GB are not reported by the usual mailbox property, and it
      seems unlikely that this will change because the VC RAM allocation has to
      remain within the bottom 1GB of the address space (the VC still uses the
      upper two bits of its addresses for cache policy) and this property cannot
      describe a non-contiguous range. Use the board revision bitfield to recognise
      when additional general-purpose RAM exists above the VC allocation. For now,
      we're running in "low peripherals" mode, so the top 64MB of 4GB RAM machines
      is inaccessible. If the VC allocation is also 64MB, that means the startup
      banner of Pi 4 will read 960MB, 1984MB or 3968MB.
      
      Also fix HAL_PhysInfo (and by implication, OS_Memory 6 and 7) to report the
      full 35-bit physical address space on Pi 4. The `range` struct filled in by
      HAL_PhysInfo has not been extended to 64-bit physical addresses because it
      describes RAM, and for now at least, RAM just squeezes into 32-bit addresses.
      9f19d29e
    • Ben Avison's avatar
      Support EMMC2 controller · b1569c4f
      Ben Avison authored
      This controller is now preferred over the legacy EMMC controller, and it is
      capable of UHS speeds (pending support in SDIODriver).
      
      Requires RiscOS/Sources/HWSupport/SD/SDIODriver!4
      b1569c4f
    • Ben Avison's avatar
      Extended IRQ support, and FIQ support · 07348d58
      Ben Avison authored
      Both still use GIC bypass mode. Assuming for now that extended GPU peripherals
      can't support FIQ without GIC (it seems as though they either all use IRQ or
      all use FIQ, and RISC OS isn't set up for there being multiple FIQ sources
      active at once).
      07348d58
    • Ben Avison's avatar
      Enable SD controller · 8aac3b72
      Ben Avison authored
      Detail:
      * Efforts to get the faster EMMC2 controller working are ongoing. In the
        meantime, this enables the backward-compatible EMMC1 controller.
      * The method required to control the activity LED appears to have changed,
        yet again. I haven't worked out how yet, so this is currently
        non-functional.
      8aac3b72
    • Ben Avison's avatar
      Get IRQs working · 068d02ad
      Ben Avison authored
      Detail:
      * For now, this uses the legacy interrupt controller, whose register layout has
        unfortunately changed in some unhelpful ways. There is also a GICv2 in the
        SoC, which we will need to transition across to in order to use some of the
        newer peripherals (including USB3 and gigabit Ethernet).
      * This requires a corresponding set of changes to start.elf: substitute all
        three instances of &E30011E7 with &E3001000.
      * FIQs are not currently supported, as the legacy interrupt controller has
        changed how these are handled. It seems likely that we'll transition to
        GIC before too long, which means it's not worth bothering to implement them
        for the legacy interrupt controller.
      068d02ad
    • Ben Avison's avatar
      Minimal read-write support for mini-UART · 932e3f57
      Ben Avison authored
      Because the mini-UART clock is derived from the core clock, and this varies
      by hardware platform and even firmware version, move the initial mailbox
      read to before UART initialisation so that this information is available.
      932e3f57
    • Ben Avison's avatar
      Peripheral physical addresses have moved again · 0821d828
      Ben Avison authored
      Also:
      * the IO region previously used only for the QA7 extensions now holds a GIC
        as well on Pi 4, so give it a more generic name
      * there's a new, second peripheral IO region to map in as well
      0821d828
  7. 02 Aug, 2019 1 commit
    • Ben Avison's avatar
      Address of mailbox given to GPU should have cacheability bits set correctly · 34d04d6b
      Ben Avison authored
      On entry to HAL_SendHostMessage, we ensure the contents of the mailbox buffer
      are flushed out to the ARM L2 cache (if applicable) and main memory. There
      were a couple of instructions to fill in the top two bits of the address
      before passing it to the VC, but they were commented out for reasons that are
      not clear.
      
      The effect of this is that the VC will look in its L1 and L2 caches for the
      data in the buffer. On Pi 1 and 0, this wouldn't be too bad, since ARM11
      didn't have its own L2 cache and would have written the data into the VC L2
      cache instead, meaning that there would only be coherencency problems if the
      VC L1 cache still contained the old contents of the address. On Pi 2-4, it's
      more risky, because the VC L2 cache could also be inconsistent with main
      memory at this point.
      
      Reinstating the top two bits doesn't appear to cause any ill effects I can
      see (tested on Pi 1 and 4), so put these instructions back in.
      
      Version 0.80. Tagged as 'HAL_BCM2835-0_80'
      34d04d6b
  8. 20 May, 2019 1 commit
    • Robert Sprowson's avatar
      Add Compute Module 3+ support · 12a389b2
      Robert Sprowson authored
      GPIO.s,hdr/BCM2835: Table of known ids updated
      SPI.s: Fix long broken compute module support (only the original CM1 would have exported SPI2 due to not checking for the new id scheme).
      Unrelated, SDIO.s: Use CallOS macro.
      
      Thanks to Chris Hall for testing this on a CM3+ 8GB model.
      
      Version 0.79. Tagged as 'HAL_BCM2835-0_79'
      12a389b2
  9. 26 Oct, 2018 1 commit
  10. 07 Jul, 2018 1 commit
    • Jeffrey Lee's avatar
      Merge SMP branch to trunk · 06491820
      Jeffrey Lee authored
      Detail:
        hdr/StaticWS - Reserve workspace for QA7 peripheral address, HAL-wide spinlock, and doorbell device
        Makefile, s/DBell - Add doorbell device implementation
        hdr/BCM2835 - Clean up dead macros, add new macros for spinlock claim/release and basic CPU detection. Define new IRQ numbers for the "QA7" peripheral.
        hdr/CastleMacros, s/Top - Generate two HAL descriptors and entry point tables: One for single-core machines and one for multi-core machines. This avoids some MP-related overheads on ARM11 models of Pi. Implement SMP HAL entry points.
        s/Interrupts - Add support for the QA7 interrupts. Although some interrupts can be flexibly routed to different cores, we currently stick with a static scheme.
        s/Messaging - Use CPUDetect macro
      Admin:
        Untested
        Requires Kernel-6_09
      
      
      Version 0.76. Tagged as 'BCM2835-0_76'
      06491820
  11. 19 Mar, 2018 1 commit
    • Jeffrey Lee's avatar
      Fix SD activity LED on 3B+ · f90ce9ec
      Jeffrey Lee authored
      Detail:
        hdr/BCM2835 - Add some new board revision values
        s/SDIO - Treat the 3B+ the same as the 3B when handling the activity LED. Also detect the Embest-manufactured CM1 and treat it the same as the Sony one.
      Admin:
        Tested on Raspberry Pi 3B+
      
      
      Version 0.74. Tagged as 'BCM2835-0_74'
      f90ce9ec
  12. 27 Jul, 2017 1 commit
  13. 11 Feb, 2017 1 commit
    • ROOL's avatar
      Transition Pi HAL to GPIO API 1.00 · d3f4d7ef
      ROOL authored
      Detail:
        Move the register accesses for GPIO to the HAL, since they are hardware specific.
        Add recognition of board types for Pi 3, Compute module 3, rev 3 Pi 0's, and the newer Pi 2's with BCM2837 on them.
      Admin:
        Based in part on a submission from Tank.
        Tested on a Pi 2. Requires corresponding GPIO module (tag GPIO-1_00-1_11_2_1 or later).
      
      Version 0.67. Tagged as 'BCM2835-0_67'
      d3f4d7ef
  14. 20 Jan, 2017 1 commit
    • Jeffrey Lee's avatar
      Add JTAG debugging support · e626e215
      Jeffrey Lee authored
      Detail:
        hdr/BCM2835 - Add switch to allow GPIOs 22-27 to be reconfigured for ARM JTAG access
        s/Top - Configure GPIOs for JTAG if switch enabled
        s/GPIO - Disable GPIO HAL device if JTAG enabled (try and avoid any software messing with the pins)
      Admin:
        Tested on Raspberry Pi 1 B, B+
      
      
      Version 0.66. Tagged as 'BCM2835-0_66'
      e626e215
  15. 10 Dec, 2016 1 commit
    • ROOL's avatar
      Report POR flag to the kernel · 3467df7b
      ROOL authored
      Detail:
        Look at the reset status register and use the HADPOR flag to influence the OSStartFlag_POR value.
        Fixes problem of OS_Byte 253 always reporting a hard reset, never a power on reset.
      Admin:
        Tested on a Pi 2.
        Submission for USB bounty.
      
      Version 0.64. Tagged as 'BCM2835-0_64'
      3467df7b
  16. 22 Oct, 2016 1 commit
  17. 09 Oct, 2016 1 commit
    • Jeffrey Lee's avatar
      Implement HAL UART API. Tidy up debug output. · b5d4e1d0
      Jeffrey Lee authored
      Detail:
        hdr/BCM2835, hdr/StaticWS, s/Debug, s/Top, s/Video - Fix up the two serial debug switches to work correctly. Disable debug by default.
        s/UART, hdr/UART - Implement HAL UART API, for the PL011 UART.
      Admin:
        Tested on Raspberry Pi 1 B
        Requires DualSerial 0.25 to work correctly
      
      
      Version 0.59. Tagged as 'BCM2835-0_59'
      b5d4e1d0
  18. 28 Mar, 2016 1 commit
    • Jeffrey Lee's avatar
      Put the other cores into a holding pattern · 56779d91
      Jeffrey Lee authored
      Detail:
        s/Top - On multi-core chips, the ARM boot stub has the other cores sat waiting in a loop near &0. Clearing RAM will inadvertantly break them out of this and most likely cause random crashes later on, so inbetween relocating the ROM and clearing RAM make sure we put the cores into a sleep loop in the HAL. Further mailbox writes can then be used to break them out of this loop, using a similar scheme to that used to break them out of the boot stub loop.
        hdr/BCM2835 - Add some register definitions from the BCM2836 docs
      Admin:
        Tested on Pi 2B, 3B
        Not currently dealing with kernel_old=1 case where all cores enter the ROM on startup
      
      
      Version 0.55. Tagged as 'BCM2835-0_55'
      56779d91
  19. 26 Mar, 2016 1 commit
    • Jeffrey Lee's avatar
      Fix SD card activity LED on Pi 3B · 3e87de33
      Jeffrey Lee authored
      Detail:
        hdr/BCM2835 - Remove mailbox definitions - use the ones exported by BCMSupport to avoid needless duplication
        hdr/StaticWS, s/Messaging, s/Top - Use the mailbox property interface to request & map in the virtual GPIO buffer (if present)
        s/SDIO - On the Pi 3B, the GPIO that was used for the SD activity GPIO is now used for a different purpose. To control the activity LED we need to go via an I2C attached GPIO extender, which itself is exposed to the ARM via the new "virtual GPIO" buffer
        s/VCHIQ - Update to use BCMSupport mailbox definitions
      Admin:
        Tested on Pi 1B, 3B
      
      
      Version 0.54. Tagged as 'BCM2835-0_54'
      3e87de33
  20. 15 Nov, 2015 1 commit
    • Jeffrey Lee's avatar
      Add basic HAL device for the official DSI display/touchscreen. Delete superfluous code. · 76db1228
      Jeffrey Lee authored
      Detail:
        Makefile, s/Touch - Basic HAL device for the official touchscreen, which just exposes the address of the buffer which the GPU periodically fills with a register dump of the touchscreen controller.
        hdr/BCM2835 - Remove old comment. Add new tag for getting the touchscreen buffer address.
        hdr/StaticWS - Remove old workspace entries. Add new entries for touchscreen.
        s/Messaging - Remove the messagebox tags which set a screen mode on startup (BCMVideo will handle that for us), and just blank the screen instead (to stop the GPU displaying a coloured square). Add tag to get the touchscreen buffer address.
        s/Top - Register touchscreen HAL device during HAL_InitDevices. Remove more old code.
      Admin:
        Tested on Raspberry Pi 1 B
      
      
      Version 0.50. Tagged as 'BCM2835-0_50'
      76db1228
  21. 26 Jul, 2015 1 commit
    • Jeffrey Lee's avatar
      Add basic HAL devices for the SPI controllers · f2a40e26
      Jeffrey Lee authored
      Detail:
        s/SPI - Basic HAL devices for the 3 SPI controllers. These expose the register addresses & IRQ numbers, and (for SPI1 & SPI2) deal with enabling/disabling the hardware and the shared IRQ line. GPIO mapping currently isn't dealt with - we don't know which pin group to use (SPI0 can use two different sets on the compute) or how many chip select lines are desired.
        Makefile - Add SPI source
        hdr/BCM2835 - Add aux SPI registers
        hdr/StaticWS - Reserve workspace for the HAL devices
        s/Top - Register new devices in HAL_InitDevices
      Admin:
        Tested on Raspberry Pi B & 2 B
      
      
      Version 0.45. Tagged as 'BCM2835-0_45'
      f2a40e26
  22. 07 Feb, 2015 1 commit
    • Jeffrey Lee's avatar
      Add workaround for Cortex-A7 errata 814220 · 2b3d4781
      Jeffrey Lee authored
      Detail:
        hdr/BCM2835 - Errata 814220 states that the Cortex-A7 set/way cache maintenance operations violate the usual operation ordering rules, such that an L2 maintenance operation which is started after an L1 operation may actually complete before it, causing data corruption if the L1 data was to be evicted to the L2 entry. Implement the suggested workaround of performing a DSB when switching cache levels, rather than just at the end of the combined L1+L2 group of operations.
        Also, fix missing 99 label that would have caused a stack imbalance in the unlikely event of encountering a processor with fully coherent caches
      Admin:
        Tested on Raspberry Pi 2
      
      
      Version 0.43. Tagged as 'BCM2835-0_43'
      2b3d4781
  23. 02 Feb, 2015 1 commit
    • Ben Avison's avatar
      Add support for Raspberry Pi Compute module and Raspberry Pi 2 · 60752490
      Ben Avison authored
      Detail:
        * Compute module support consists of eMMC support in the SDHCI driver. The
          eMMC chip on the Compute module only works reliably if under-clocked to
          25 MHz.
        * Pi 1 vs Pi 2 differences are selected at runtime by checking the CPU ID,
          so a single ROM image will work with both boards.
        * Added ARMv7 cache maintenance routine for use on Pi 2.
        * The physical address of the peripherals has moved in Pi 2 to make space
          for the 1 GB of RAM.
        * The ARM physical address space is mapped differently onto the GPU
          address space in Pi 2 because the ARM now uses the L2 cache that comes
          with the Cortex-A7 instead of the GPU's L2 cache.
        * Still waiting for confirmation on the board revision ID that will be
          used for Pi 2, so may require further tweaks for production releases.
      
      
      Version 0.40. Tagged as 'BCM2835-0_40'
      60752490
  24. 19 Jun, 2014 1 commit
    • Jeffrey Lee's avatar
      Add support code required for DWCDriver 'FIQ fix' · af7cf4e9
      Jeffrey Lee authored
      Detail:
        hdr/BCM2835, hdr/USB, s/USB - Update HAL_USBControllerInfo to return the MPHI address & IRQ number
        s/Interrupts - Add some missing memory barriers. Change FIQ enable/disable calls to not alter IRQ masking of the interrupt - simplifies the code and avoids any ordering issues with code that switches interrupts between IRQ & FIQ
        s/Timers - Add missing memory barrier
      Admin:
        Tested on Raspberry Pi
        Requires Kernel-5_35-4_79_2_227 to build
      
      
      Version 0.34. Tagged as 'BCM2835-0_34'
      af7cf4e9
  25. 22 Jan, 2013 1 commit
    • Jeffrey Lee's avatar
      Implement HAL_IRQMax · 495018ca
      Jeffrey Lee authored
      Detail:
        hdr/BCM2835 - Add definition for highest IRQ number
        s/Boot, s/Interrupts - Added HAL_IRQMax implementation, to ensure correct functionality with latest Kernel
      Admin:
        Tested on 256MB Pi model B
        Requires Kernel-5_35-4_79_2_182
      
      
      Version 0.29. Tagged as 'BCM2835-0_29'
      495018ca
  26. 18 Sep, 2012 1 commit
    • Jeffrey Lee's avatar
      Add a video HAL device to allow BCMVideo to determine which DMA channel it can use for render ops · 47a0e5d7
      Jeffrey Lee authored
      Detail:
        hdr/StaticWS, s/Top, s/Video - Added a simple VDU HAL device that exposes a DMA channel to BCMVideo for use with GraphicsV_Render
        hdr/BCM2835 - Don't allow DMA channel 12 to be used; latest firmware seems to have a bug which claims its free when in reality it isn't.
        s/Messaging, s/DMA - Adjust DMA init to allow the video device to claim a DMA channel before the DMA devices are initialised
      Admin:
        Tested on Raspberry Pi with high processor vectors
      
      
      Version 0.25. Tagged as 'BCM2835-0_25'
      47a0e5d7
  27. 10 Sep, 2012 1 commit
    • Jeffrey Lee's avatar
      Use BCS1 instead of BCS0 for IIC when running on rev 2 boards · a1c4df2f
      Jeffrey Lee authored
      Detail:
        hdr/BCM2835, hdr/StaticWS, s/IIC - On rev 2 boards the usage of BSC0 and BSC1 have been swapped, such that BSC1 is now sent to the expansion header instead of BSC0.
        To allow RISC OS to continue to work with clock chips and other hardware fitted to the header, expose BSC1 to RISC OS if on a rev 2 board, or BSC0 if on a rev 1.
      Admin:
        Changes received from Dave Higton
        Tested by Dave on rev 1 & rev 2 boards, with IIC devices
        Tested by me on rev 1 board (with no IIC devices fitted)
      
      
      Version 0.24. Tagged as 'BCM2835-0_24'
      a1c4df2f
  28. 02 Sep, 2012 1 commit
    • Jeffrey Lee's avatar
      Strip out video code & on-screen debug · d56f8a14
      Jeffrey Lee authored
      Detail:
        Makefile, s/Display - Deleted on-screen debug code
        hdr/BCM2835, hdr/StaticWS, s/IIC, s/Messaging, s/Stubs, s/Top, s/UART - Strip out calls to on-screen debug code, and a few bits of video code
        s/Video - Video code removed and replaced with stub functions similar to other HALs. Only remaining useful code is HAL_Video_StartupMode, which in time should probably be moved to BCMVideo as well.
      Admin:
        Tested on Raspberry Pi with high processor vectors
      
      
      Version 0.21. Tagged as 'BCM2835-0_21'
      d56f8a14
  29. 28 Aug, 2012 1 commit
    • Ben Avison's avatar
      Addition of I2C support · ade8e2c2
      Ben Avison authored
      Detail:
        Implementation of the high-level HAL IIC interface provided by Dave Higton.
      Admin:
        Checked it builds and runs at ROOL.
      
      Version 0.20. Tagged as 'BCM2835-0_20'
      ade8e2c2
  30. 02 Aug, 2012 1 commit
    • Jeffrey Lee's avatar
      Add GPIO & VCHIQ HAL devices. Fix FlushDataCache macro to perform a clean &... · 3b36df75
      Jeffrey Lee authored
      Add GPIO & VCHIQ HAL devices. Fix FlushDataCache macro to perform a clean & invalidate instead of just an invalidate.
      
      Detail:
        s/GPIO - Basic implementation of the GPIO HAL device to allow the GPIO module to detect the board type
        s/VCHIQ, hdr/StaticWS - New VCHIQ HAL device which exposes the functionality required by the work-in-progress VCHIQ driver.
        Makefile, s/Top - Hook up the new files/devices
        hdr/BCM2835 - Make the FlushDataCache macro perform a clean & invalidate, to match the behaviour of FlushDataCacheRange
      Admin:
        Tested on Raspberry Pi with high processor vectors
      
      
      Version 0.17. Tagged as 'BCM2835-0_17'
      3b36df75
  31. 22 Jul, 2012 1 commit