- 02 Feb, 2015 1 commit
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Ben Avison authored
Detail: * Compute module support consists of eMMC support in the SDHCI driver. The eMMC chip on the Compute module only works reliably if under-clocked to 25 MHz. * Pi 1 vs Pi 2 differences are selected at runtime by checking the CPU ID, so a single ROM image will work with both boards. * Added ARMv7 cache maintenance routine for use on Pi 2. * The physical address of the peripherals has moved in Pi 2 to make space for the 1 GB of RAM. * The ARM physical address space is mapped differently onto the GPU address space in Pi 2 because the ARM now uses the L2 cache that comes with the Cortex-A7 instead of the GPU's L2 cache. * Still waiting for confirmation on the board revision ID that will be used for Pi 2, so may require further tweaks for production releases. Version 0.40. Tagged as 'BCM2835-0_40'
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- 30 Oct, 2014 1 commit
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Ben Avison authored
Version 0.39. Tagged as 'BCM2835-0_39'
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- 14 Jul, 2014 1 commit
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Ben Avison authored
Detail: The activity GPIO pin has been reassigned and its sense is inverted, compared to earlier boards. More importantly, the SD card detect pin has been removed entirely, so we need to signal to the SD stack to use its new timeout-based state machine (rather than polling for card presence). Admin: Already in use in RC12a. Version 0.35. Tagged as 'BCM2835-0_35'
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- 01 Jul, 2012 1 commit
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Ben Avison authored
Detail: * Engage the GPIO controller's pull-up resistors on SDCLK, CMD and DAT0-DAT3. In tests, this seems to address the worst of the unreliability we have seen previously. * Remove the entry to change the bus between push-pull and open-drain modes. The BCM2835 simply doesn't seem to be able to do this. Fortunately, all the cards I have tested seem to be OK with the GPIO controller's pull-up on the CMD line (however strong that is - it's undocumented) engaged at all times. * Time a dummy command in order to calculate the speed of the input clock to the SD controller block (there doesn't appear to be any way to read its speed directly!) This is necessary because recent versions of the firmware have not only changed the default clock speed, but even made it a user-configurable option in config.txt. It's very important that we know how fast it is - if we set the dividers so SDCLK is too slow, then the workaround for the register write bug won't work, too fast and we overclock the cards, potentially damaging them. * Re-enable high speed mode. As long as we don't use the High Speed Enable bit in Host Control 1 (see change in SDIODriver 0.03) this seems to work for me. Admin: Tested against my collection of test cards on a Raspberry Pi with the firmware from the 2012-06-22 commit on github, and with init_emmc_clock=100000000 in config.txt (though other values, or the absence of that line, or the entire file, should also work). The only issues I had appeared to be due to mechanical problems with the SD socket, and went away after the card was reseated one or more times. Version 0.10. Tagged as 'BCM2835-0_10'
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- 15 Jun, 2012 1 commit
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Ben Avison authored
Detail: * Bugfix to HAL_FIQDisableAll - it wasn't clearing the FIQ register (would only have caused trouble in practice if the same device was subsequently enabled as an IRQ). * Added a load of memory barriers to s.Interrupts and s.Timers to conform to the requirement stated in 1.3 of the datasheet. * Added a HAL device for the Arasan SDHCI controller. Note that this does not currently work reliably, and results vary from card to card. High speed support is currently disabled until we are able to verify that it works reliably. * Added a sprinkling of "GET Hdr:ListOpts" because the space reserved for the SDHCI HAL device in hdr.StaticWS is determined by including Hdr:HALDevice and Hdr:SDHCIDevice, which need it. * When support for saving "CMOS" to the SD card is added, the ROM image file (kernel.img) is the only one we can count on the bootloader installing in memory, so I think we're going to have to work using t...
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