1. 24 May, 2012 1 commit
  2. 23 May, 2012 1 commit
    • Ben Avison's avatar
      Complete rework of timer and interrupt code · 2579b887
      Ben Avison authored
      Detail:
       * Moved interrupt and timer code out of s.Stubs - they're not stubs any more.
       * Rewrote timer and counter code to use GPU system timer 1 for our Timer0
         rather than the ARM timer. This is recommended in the Broadcom datasheet
         because it's driven from the APB clock and so its speed will vary in
         reduced or low power mode.
       * HAL_CounterDelay now, well, does a delay!
       * Added a Timer1, driven from GPU system timer 3 - common code with Timer0.
       * Reshuffled device numbers so the GPU interrupts are at the bottom. This
         works better for FIQs and makes Timer0 the lowest priority interrupt.
       * Higher device numbers are now consistently treated as higher priority.
       * Stopped using bits 8-31 of the basic interrupt registers. These can't be
         masked, so they cause the kernel to lock up if generated, which happens
         if the GPU interrupt which they alias is generated (which appears to
         include the timers even though this is not documented).
       * Added definitions for all the interrupts, including those redacted from the
         datasheet - we need them at least for timers, USB and SD.
       * Stopped HAL_IRQClear from doing anything - this interrupt controller
         doesn't do latching. To acknowledge timer interrupts, you should use
         HAL_TimerIRQClear (and HAL_IRQClear too for compatibility with other ports).
       * Implemented HAL_IRQStatus and all the FIQ control routines.
       * Offsets to interrupt controller registers now use symbolic names.
       * Replaced some hard spaces in sources with normal ones.
      Admin:
        Tested on a beta Raspberry Pi. Confirmed that interrupt handlers for both
        ARM and GPU sources can both be operational simultaneuosly. However, the FIQ
        code has not been tested. Timer0 is verified as running at the correct
        speed and reporting a count *down* in the correct range (not a count up as
        some previous versions did). HAL_CounterDelay appears correct also.
      
      Version 0.04. Tagged as 'BCM2835-0_04'
      2579b887
  3. 22 May, 2012 1 commit
    • John Ballance's avatar
      Boots with May17th start.elf · bfd45048
      John Ballance authored
      Detail:
         Recent changes in the broadcom startup code now accomodated. frame buffer
         will now determine whether it is L2 cached or not, and be set up accordingly.
         ATAGs not currently read, so ram size defaulted.
        ** note that there will be further updates to this over the following days
        ** trackikng startup code changes.
         added HAL_TimerIRQClear entry
      Admin:
        (highlight level of testing that has taken place)
        (bugfix number if appropriate)
      
      
      Version 0.03. Tagged as 'BCM2835-0_03'
      bfd45048
  4. 20 May, 2012 1 commit
    • John Ballance's avatar
      Update of HAL to incorporate separate development of HAL by J Ballance · 71e5f9c7
      John Ballance authored
        Will now compile against initial developemnt start.elf, and against the
        start.elf in general release at this date. (compile switch UseALBlob in
        hdr.BCM2835). Extended header defs, Updated IRQ stuff, HAL_FramebufferAddress
        Reworked Timers, + a number of other bits. Still work in progress.
      Detail:
        (list files and functions that have changed)
      Admin:
        Compiled and working - as far as it goes -. Will enable use with the current
        start.elf, and is (subject to any minor changes introduced) ready for use with the
        version due for release shortly which will provide the correct transparency operation,
        and a better aligned frame buffer
      
      Version 0.02. Tagged as 'BCM2835-0_02'
      71e5f9c7
  5. 10 May, 2012 1 commit