Commit fa58a55a authored by Jeffrey Lee's avatar Jeffrey Lee
Browse files

Add extra memory barrier

Detail:
  s/DMA - Although there are already plenty of memory barriers present to deal with the BCM2835's dodgy peripheral interface, code examination suggests one extra barrier is needed to make sure things will work correctly once the default NCB cache policy is Normal, non-cacheable rather than Device.
Admin:
  Tested on Raspberry Pi 1


Version 0.47. Tagged as 'BCM2835-0_47'
parent 765f5293
/* (0.46)
/* (0.47)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.46
#define Module_MajorVersion_CMHG 0.47
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 05 Aug 2015
#define Module_Date_CMHG 14 Aug 2015
#define Module_MajorVersion "0.46"
#define Module_Version 46
#define Module_MajorVersion "0.47"
#define Module_Version 47
#define Module_MinorVersion ""
#define Module_Date "05 Aug 2015"
#define Module_Date "14 Aug 2015"
#define Module_ApplicationDate "05-Aug-15"
#define Module_ApplicationDate "14-Aug-15"
#define Module_ComponentName "BCM2835"
#define Module_ComponentPath "mixed/RiscOS/Sources/HAL/BCM2835"
#define Module_FullVersion "0.46"
#define Module_HelpVersion "0.46 (05 Aug 2015)"
#define Module_LibraryVersionInfo "0:46"
#define Module_FullVersion "0.47"
#define Module_HelpVersion "0.47 (14 Aug 2015)"
#define Module_LibraryVersionInfo "0:47"
......@@ -779,6 +779,7 @@ DMAL_CurtailListTransfer ROUT
MOV lr, #0
STR lr, [ip, #DMACB_NEXTCONBK] ; Break chain
20
DoMemBarrier lr ; Ensure write has completed before we resume
; Resume transfer
STR a3, [a2, #DMACH_CS]
DoMemBarrier lr
......
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